 | This article is written like a manual or guide.(June 2014) |
The Atmel AVR instruction set is the machine language for the Atmel AVR, a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage.
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There are 32 general-purpose 8-bit registers, R0–R31. All arithmetic and logic operations operate on those registers; only load and store instructions access RAM.
A limited number of instructions operate on 16-bit register pairs. The lower-numbered register of the pair holds the least significant bits and must be even-numbered. The last three register pairs are used as pointer registers for memory addressing. They are known as X (R27:R26), Y (R29:R28) and Z (R31:R30). Postincrement and predecrement addressing modes are supported on all three. Y and Z also support a six-bit positive displacement.
Instructions which allow an immediate value are limited to registers R16–R31 (8-bit operations) or to register pairs R25:R24–R31:R30 (16-bit operations ADIW and SBIW). Some variants of the MUL operation are limited to eight registers, R16 through R23.
In addition to these 32 general-purpose registers, the CPU has a few special-purpose registers:
The status register bits are:
There are two special cases which exist to facilitate multi-byte arithmetic:
INC and DEC instructions do not modify the carry flag, so they may be used to loop over arbitrary-precision arithmetic operands. [1] : 84, 101 CPC, SBC and SBCI (compare/subtract with carry) instructions do not set the Z flag when the result is zero, but only clear it if the result is non-zero. [1] : 79,147,149 For fixed precision multi-byte comparisons, implemented with an unrolled CP; CPC; CPC; CPC sequence, this produces a zero flag which is set only if the entire difference is zero.The following address spaces are available:
The first 64 I/O registers are accessible through both the I/O and the data address space. They have therefore two different addresses. These are usually written as "0x00 (0x20)" through "0x3F (0x5F)", where the first item is the I/O address and the second, in parentheses, the data address.
The special-purpose CPU registers, with the exception of PC, can be accessed as I/O registers. Some registers (RAMPX, RAMPY) may not be present on machines with less than 64 KiB of addressable memory.
| Register | I/O address | Data address |
|---|---|---|
| SREG | 0x3F | 0x5F |
| SP | 0x3E:0x3D | 0x5E:0x5D |
| EIND | 0x3C | 0x5C |
| RAMPZ | 0x3B | 0x5B |
| RAMPY | 0x3A | 0x5A |
| RAMPX | 0x39 | 0x59 |
| RAMPD | 0x38 | 0x58 |
A typical ATmega memory map may look like:
| Data address | I/O address | Contents |
|---|---|---|
| 0x0000 – 0x001F | Registers R0 – R31 | |
| 0x0020 – 0x003F | 0x00 – 0x1F | I/O registers (bit-addressable) |
| 0x0040 – 0x005F | 0x20 – 0x3F | I/O registers (not bit-addressable) |
| 0x0060 – 0x00FF | Extended I/O registers (memory-mapped I/O only) | |
| 0x0100 – RAMEND | Internal SRAM |
where RAMEND is the last RAM address. In parts lacking extended I/O the RAM would start at 0x0060.
Arithmetic operations work on registers R0–R31 but not directly on RAM and take one clock cycle, except for multiplication and word-wide addition (ADIW and SBIW) which take two cycles.
RAM and I/O space can be accessed only by copying to or from registers. Indirect access (including optional postincrement, predecrement or constant displacement) is possible through registers X, Y, and Z. All accesses to RAM takes two clock cycles. Moving between registers and I/O is one cycle. Moving eight or sixteen bit data between registers or constant to register is also one cycle. Reading program memory (LPM) takes three cycles.
Instructions are one 16-bit long word, save for those including a 16-bit or 22-bit address, which take two words.
There are two types of conditional branches: jumps to address and skips. Conditional branches (BRxx) can test an ALU flag and jump to specified address. Skips (SBxx) test an arbitrary bit in a register or I/O and skip the next instruction if the test was true.
In the following:
| Arithmetic | Bit & Others | Transfer | Jump |
|---|---|---|---|
ADDRd,RrADCRd,RrADIWRp+1:Rp,K6SUBRd,RrSUBIRdh,K8SBCRd,RrSBCIRdh,K8SBIWRp+1:Rp,K6INCRdDECRdANDRd,RrANDIRdh,K8ORRd,RrORIRdh,K8COMRdNEGRdCPRd,RrCPCRd,RrCPIRdh,K8SWAPRdLSRRdRORRdASRRdMULRd,RrMULSRdh,RrhMULSURdq,RrqFMULRdq,RrqFMULSRdq,RrqFMULSURdq,Rrq | BSETsBCLRsSBIIO5,bCBIIO5,bBSTRd,bBLDRd,bNOPBREAKSLEEPWDR | MOVRd,RrMOVWRd+1:Rd,Rr+1:RrINRd,IO6OUTIO6,RrPUSHRrPOPRrLDIRdh,K8LDSRd,D16LDRd,XLDDRd,YZ+K6LDRd,-XYZLDRd,XYZ+STSD16,RrSTX,RrSTDYZ+K6,RrST-XYZ,RrSTXYZ+,RrLPMLPMRd,ZLPMRd,Z+ELPMELPMRd,ZELPMRd,Z+SPM | RJMPS12IJMPEIJMPJMPP22 |
| Call | |||
RCALLS12ICALLEICALLCALLP22RETRETI | |||
| Branch | |||
CPSERd,RrSBRCRr,bSBRSRr,bSBICIO5,bSBISIO5,bBRBCs,S7BRBSs,S7 |
Not all instructions are implemented in all Atmel AVR controllers. This is the case of the instructions performing multiplications, extended loads/jumps/calls, long jumps, and power control.
The optional instructions may be grouped into three categories:
While higher-end processors tend to have both more capable cores and more memory, the presence of one does not guarantee the presence of the other.
Beginning with the original "classic" core, enhancements are organized into the following levels, each of which includes all the preceding:
LPM instruction, which is equivalent to LPM r0,Z.MOVW instruction for moving register pairs, and the more general form of the LPM instruction (LPM Rd,Z and LPM Rd,Z+) which permit an arbitrary destination register and auto-increment of the Z pointer.XCH), load-and-set, load-and-clear, and load-and-toggle. These help coordinate with direct memory access peripherals, notably a USB controller.Less capable than the "classic" CPU cores are two subsets: the "AVR1" core, and the "AVR tiny". Confusingly, "ATtiny" branded processors have a variety of cores, including AVR1 (ATtiny11, ATtiny28), classic (ATtiny22, ATtiny26), classic+ (ATtiny24) and AVRtiny (ATtiny20, ATtiny40).
The AVR1 subset was not popular and no new models have been introduced since 2000. It omits all RAM except for the 32 registers mapped at address 0–31 and the I/O ports at addresses 32–95. The stack is replaced by a 3-level hardware stack, and the PUSH and POP instructions are deleted. All 16-bit operations are deleted, as are IJMP, ICALL, and all load and store addressing modes except indirect via Z.
A second, more successful attempt to subset the AVR instruction set is the "AVR tiny" core.
The most significant change is that the AVRtiny core omits registers R0–R15. The registers are also not memory-mapped, with I/O ports from 0–63 and general-purpose RAM beginning at address 64. The 16-bit arithmetic operations (ADIW, SBIW) are omitted, as are the load/store with displacement addressing modes (Y+d, Z+d), but the predecrement and postincrement addressing modes are retained. The LPM instruction is omitted; instead program ROM is mapped to the data address space and may be accessed with normal load instructions.
Finally, the AVRtiny core deletes the 2-word LDS and STS instructions for direct RAM addressing, and instead uses the opcode space previously assigned to the load/store with displacement instructions for new 1-word LDS and STS instructions which can access the first 128 locations of general-purpose RAM, addresses 0x40 to 0xBF. (The IN and OUT instructions provide direct access to I/O space from 0 to 0x3F.)
The smallest cores have ≤256 bytes of data address space (meaning ≤128 bytes of RAM after I/O ports and other reserved addresses are removed) and ≤8192 bytes (8 KiB) of program ROM. These have only an 8-bit stack pointer (in SPL), and only support the 12-bit relative jump/call instructions RJMP/RCALL. (Because the AVR program counter counts 16-bit words, not bytes, a 12-bit offset is sufficient to address 213 bytes of ROM.)
Additional memory addressing capabilities are present as required to access available resources:
JUMP and CALL instructions. (Some early models suffer an erratum if a skip instruction is followed by a 2-word instruction.)ELPM instruction and corresponding RAMPZ register. LPM instructions zero-extend the ROM address in Z; ELPM instructions prepend the RAMPZ register for high bits. This is not the same thing as the more general LPM instruction; there exist "classic" models with only the zero-operand form of ELPM (ATmega103 and at43usb320). When auto-increment is available (most models), it updates the entire 24-bit address including RAMPZ.EIJMP and EICALL which use EIND:Z as the destination address. (The previous IJMP and ICALL instructions use zero-extended Z.)LDS/STS. Unlike ROM access, there are no distinct "extended" instructions; instead the RAMP registers are used unconditionally.Three instructions are present only on models which have the corresponding hardware facility
SPM for storing to flash ROM, is present only on processors with flash ROM (most of them)BREAK for invoking the on-chip debugger, is omitted on some small models without on-chip debugger supportDES for performing Data Encryption Standard rounds, is present on XMEGA models with DES accelerator supportArchitectures other than AVR1 are named according to avr-libc conventions. [2]
| Family | Members | Arithmetic | Branches | Transfers | Bit-Wise | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Minimal AVR1 Core |
|
|
|
|
| ||||||||||||
| Classic Core up to 8K Program Space ("AVR2") |
| new instructions:
| new instructions:
| new instructions:
| (nothing new) | ||||||||||||
| AVR2, with MOVW and LPM instructions ("AVR2.5") |
| (nothing new) | (nothing new) | new instructions:
| (nothing new) | ||||||||||||
| Classic Core with up to 128K ("AVR3") |
| (nothing new) | new instructions:
| new instructions:
| (nothing new) | ||||||||||||
| Enhanced Core with up to 8K ("AVR4") |
| new instructions:
| (nothing new) | new instructions:
| (nothing new) | ||||||||||||
| Enhanced Core with up to 128K ("AVR5", "AVR5.1") |
| (nothing new) | new instruction:
| (nothing new) | new instructions:
| ||||||||||||
| Enhanced Core with up to 4M ("AVR5" and "AVR6") |
| (nothing new) | new instructions:
| (nothing new) | (nothing new) | ||||||||||||
| XMEGA Core ("avrxmega" 2-6) | ATxmega series | new instructions:
| (nothing new) | new instructions (from second revision silicon - AU,B,C parts)
| (nothing new) | ||||||||||||
| Reduced AVRtiny Core ("avrtiny10") |
| (Identical to minimal core, except for reduced CPU register set a ) | (Identical to classic core with up to 8K, except for reduced CPU register set a ) | Identical to classic core with up to 8K, with the following exceptions:
| (Identical to enhanced core with up to 128K, except for reduced CPU register set a ) |
Bit assignments:
The Atmel AVR uses many split fields, where bits are not contiguous in the instruction word. The load/store with offset instructions are the most extreme example where a 6-bit offset is broken into three pieces.
| 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Instruction |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NOP |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D D D D | R R R R | MOVW Rd,Rr Move register pair | ||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | d d d d | r r r r | MULS Rd,Rr | ||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | d d d | 0 | r r r | MULSU Rd,Rr | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | d d d | 1 | r r r | FMUL Rd,Rr | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | d d d | u | r r r | FMULS(U) Rd,Rr | ||||
| 0 | 0 | opcode | r | d d d d d | r r r r | 2-operand instructions | ||||||||||
| 0 | 0 | 0 | c̅y̅ | 0 | 1 | r | d d d d d | r r r r | CPC/CP Rd,Rr | |||||||
| 0 | 0 | 0 | c̅y̅ | 1 | 0 | r | d d d d d | r r r r | SBC/SUB Rd,Rr | |||||||
| 0 | 0 | 0 | cy | 1 | 1 | r | d d d d d | r r r r | ADD/ADC Rd,Rr (LSL/ROL Rd when Rd=Rr) | |||||||
| 0 | 0 | 0 | 1 | 0 | 0 | r | d d d d d | r r r r | CPSE Rd,Rr | |||||||
| 0 | 0 | 1 | 0 | 0 | 0 | r | d d d d d | r r r r | AND Rd,Rr | |||||||
| 0 | 0 | 1 | 0 | 0 | 1 | r | d d d d d | r r r r | EOR Rd,Rr | |||||||
| 0 | 0 | 1 | 0 | 1 | 0 | r | d d d d d | r r r r | OR Rd,Rr | |||||||
| 0 | 0 | 1 | 0 | 1 | 1 | r | d d d d d | r r r r | MOV Rd,Rr | |||||||
| 0 | 0 | 1 | 1 | K K K K | d d d d | K K K K | CPI Rd,K | |||||||||
| 0 | 1 | opc | K K K K | d d d d | K K K K | Register-immediate operations | ||||||||||
| 0 | 1 | 0 | c̅y̅ | K K K K | d d d d | K K K K | SBCI/SUBI Rd,K | |||||||||
| 0 | 1 | 1 | 0 | K K K K | d d d d | K K K K | ORI Rd,K SBR Rd,K | |||||||||
| 0 | 1 | 1 | 1 | K K K K | d d d d | K K K K | ANDI Rd,K CBR Rd,K | |||||||||
| 1 | 0 | k | 0 | k k | s | d d d d d | y | k k k | LDD/STD Rd through Z+k or Y+k | |||||||
| 1 | 0 | 0 | 1 | 0 | 0 | s | d d d d d | opcode | Load/store operations | |||||||
| 1 | 0 | 0 | 1 | 0 | 0 | s | d d d d d | 0 | 0 | 0 | 0 | LDS rd,i/STS i,rd | ||||
| 16-Bit immediate SRAM address i | ||||||||||||||||
| 1 | 0 | 0 | 1 | 0 | 0 | s | d d d d d | y | 0 | 0 | 1 | LD/ST Rd through Z+/Y+ | ||||
| 1 | 0 | 0 | 1 | 0 | 0 | s | d d d d d | y | 0 | 1 | 0 | LD/ST Rd through −Z/−Y | ||||
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | d d d d d | 0 | 1 | q | 0 | LPM/ELPM Rd,Z | ||||
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | d d d d d | 0 | 1 | q | 1 | LPM/ELPM Rd,Z+ | ||||
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | d d d d d | 0 | 1 | 0 | 0 | XCH Z,Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | d d d d d | 0 | 1 | 0 | 1 | LAS Z,Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | d d d d d | 0 | 1 | 1 | 0 | LAC Z,Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | d d d d d | 0 | 1 | 1 | 1 | LAT Z,Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 0 | s | d d d d d | 1 | 1 | 0 | 0 | LD/ST Rd through X | ||||
| 1 | 0 | 0 | 1 | 0 | 0 | s | d d d d d | 1 | 1 | 0 | 1 | LD/ST Rd through X+ | ||||
| 1 | 0 | 0 | 1 | 0 | 0 | s | d d d d d | 1 | 1 | 1 | 0 | LD/ST Rd through −X | ||||
| 1 | 0 | 0 | 1 | 0 | 0 | s | d d d d d | 1 | 1 | 1 | 1 | POP/PUSH Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 0 | opcode | One-operand instructions: | ||||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 0 | 0 | 0 | 0 | COM Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 0 | 0 | 0 | 1 | NEG Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 0 | 0 | 1 | 0 | SWAP Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 0 | 0 | 1 | 1 | INC Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 0 | 1 | 0 | 0 | (reserved) | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 0 | 1 | 0 | 1 | ASR Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 0 | 1 | 1 | 0 | LSR Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 0 | 1 | 1 | 1 | ROR Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | B̅ | b b b | 1 | 0 | 0 | 0 | SEx/CLx Status register clear/set bit | ||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | opcode | 1 | 0 | 0 | 0 | Zero-operand instructions | |||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | RET |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | RETI |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | x | 1 | 0 | 0 | 0 | (reserved) |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | x | x | 1 | 0 | 0 | 0 | (reserved) |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | SLEEP |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | BREAK |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | WDR |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | (reserved) |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | q | 1 | 0 | 0 | 0 | LPM/ELPM |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | SPM |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | SPM Z+ |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | c | 0 | 0 | 0 | e | 1 | 0 | 0 | 1 | Indirect jump/call to Z or EIND:Z |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 1 | 0 | 1 | 0 | DEC Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | k k k k | 1 | 0 | 1 | 1 | DES round k | |||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | k k k k k | 1 | 1 | c | k | JMP/CALL abs22 | ||||
| k k k k k k k k k k k k k k k k | ||||||||||||||||
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | k k | p p | k k k k | ADIW Rp,uimm6 | |||||
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | k k | p p | k k k k | SBIW Rp,uimm6 | |||||
| 1 | 0 | 0 | 1 | 1 | 0 | B | 0 | a a a a a | b b b | CBI/SBI a,b (clear/set I/O bit) | ||||||
| 1 | 0 | 0 | 1 | 1 | 0 | B | 1 | a a a a a | b b b | SBIC/SBIS a,b (I/O bit test) | ||||||
| 1 | 0 | 0 | 1 | 1 | 1 | r | d d d d d | r r r r | MUL, unsigned: R1:R0 = Rr × Rd | |||||||
| 1 | 0 | 1 | 1 | s | a a | d d d d d | a a a a | IN/OUT to I/O space | ||||||||
| 1 | 1 | 0 | c | 12 bit signed offset | RJMP/RCALL to PC + simm12 | |||||||||||
| 1 | 1 | 1 | 0 | K K K K | d d d d | K K K K | LDI Rd,K | |||||||||
| 1 | 1 | 1 | 1 | 0 | B̅ | 7-bit signed offset | b b b | Conditional branch on status register bit | ||||||||
| 1 | 1 | 1 | 1 | 1 | 0 | s | d d d d d | 0 | b b b | BLD/BST register bit to STATUS.T | ||||||
| 1 | 1 | 1 | 1 | 1 | 1 | B | d d d d d | 0 | b b b | SBRC/SBRS skip if register bit equals B | ||||||
| 1 | 1 | 1 | 1 | 1 | x | x | d d d d d | 1 | b b b | (reserved) | ||||||
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