C to HDL

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C to HDL tools convert C language or C-like computer code into a hardware description language (HDL) such as VHDL or Verilog. The converted code can then be synthesized and translated into a hardware device such as a field-programmable gate array. Compared to software, equivalent designs in hardware consume less power (yielding higher performance per watt) and execute faster with lower latency, more parallelism and higher throughput. However, system design and functional verification in a hardware description language can be tedious and time-consuming, so systems engineers often write critical modules in HDL and other modules in a high-level language and synthesize these into HDL through C to HDL or high-level synthesis tools.

Contents

C to RTL is another name for this methodology. RTL refers to the register transfer level representation of a program necessary to implement it in logic.

History

Early development on C to HDL was done by Ian Page, Charles Sweeney and colleagues at Oxford University in the 1990s who developed the Handel-C language. They commercialized their research by forming Embedded Solutions Limited (ESL) in 1999 which was renamed Celoxica in September 2000. In 2008, the embedded systems departments of Celoxica was sold to Catalytic for $3 million and which later merged to become Agility Computing. [1] In January 2009, Mentor Graphics acquired Agility's C synthesis assets. [2] Celoxica continues to trade concentrating on hardware acceleration in the financial and other industries. [3]

Applications

C to HDL techniques are most commonly applied to applications that have unacceptably high execution times on existing general-purpose supercomputer architectures. Examples include bioinformatics, computational fluid dynamics (CFD),[ clarification needed ] financial processing, and oil and gas survey data analysis. Embedded applications requiring high performance or real-time data processing are also an area of use. System-on-chip (SoC) design may also take advantage of C to HDL techniques.

C-to-VHDL compilers are very useful for large designs or for implementing code that might change in the future. Designing a large application entirely in HDL may be very difficult and time-consuming; the abstraction of a high level language for such a large application will often reduce total development time. Furthermore, an application coded in HDL will almost certainly be more difficult to modify than one coded in a higher level language. If the designer needs to add new functionality to the application, adding a few lines of C code will almost always be easier than remodeling the equivalent HDL code.

Flow to HDL tools have a similar aim, but with flow rather than C-based design.

Example tools

See also

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References

  1. ↑ Clarke, Peter (1 April 2008). "Celoxica sells EDA business to Catalytic for $3 million". EE Times.
  2. ↑ Dylan McGrath (22 January 2009). "Mentor buys Agility's C synthesis assets". EETimes.com.
  3. ↑ Celoxica Ltd (22 January 2011). "Celoxica Ltd 'About Us'". Celoxica.com. Archived from the original on 16 January 2011. Retrieved 22 January 2011.
  4. ↑ "SPARK: High-Level Synthesis using Parallelizing Compiler Techniques". Archived from the original on 2009-10-24. Retrieved 2020-07-11.
  5. ↑ "VLSI CAD Group Index of Useful Tools". Archived from the original on 2011-07-19. Retrieved 2017-07-28.{{cite web}}: CS1 maint: bot: original URL status unknown (link)
  6. ↑ "Home". myhdl.org.
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