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Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS. A few commercial applications may export MEMS designs in Verilog-A format.
Verilog-A was created out of a need to standardize the Spectre behavioral language in face of competition from VHDL (an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST). Open Verilog International (OVI, the body that originally standardized Verilog) agreed to support the standardization, provided that it was part of a plan to create Verilog-AMS — a single language covering both analog and digital design. Verilog-A was an all-analog subset of Verilog-AMS that was the first phase of the project.
There was considerable delay (possibly procrastination) between the first Verilog-A language reference manual and the full Verilog-AMS, and in that time Verilog moved to the IEEE, leaving Verilog-AMS behind at Accellera.
The email log from AD 2000 can be found here.
Verilog-A standard does not exist stand-alone - it is part of the complete Verilog-AMS standard. Its LRM is available at the Accellera website. [1] However, the initial and subsequent releases can be found here, with what will probably be the final release here since future work will leverage the new net-type capabilities in SystemVerilog. Built-in types like "wreal" in Verilog-AMS will become user-defined types in SystemVerilog more in line with the VHDL methodology.
A subset of Verilog-A can be translated automatically to the C programming language using the Automatic Device Model Synthesizer (ADMS). This feature is used for example to translate the BSIM Verilog-A transistor models, which are no more released in C, for use in simulators like ngspice. [2]
This first example gives a first demonstration of modeling in Verilog-A:
`include"constants.vams"`include"disciplines.vams"moduleexample(a,b,c,d,e,f);parameterrealR=1m;parameterrealC=1u;parameterrealL=1u;parameterintegergain=2;inputa;outputb;inoutc,d,e,f;electricala,b,c,d,e,f;analogbegin// Modelling lumped elements//ResistorV(c,d)<+R*I(c,d);//Inductor// Multiple current or voltage assignments are accumulatedV(c,d)<+L*ddt(I(c,d));//CapacitorI(e,f)<+C*ddt(V(e,f));// Simple amplifier// Voltages are referenced to ground if no second node is givenV(b)<+gain*V(a);endendmoduleThis Verilog-AMS example implements an ideal diode, by defining the current through the branch (a,c) depending on voltage at branch terminals (a), (c), and the ambient temperature of the simulated circuit:
// Ideal Diodemodulediode(a,c);inouta,c;electricala,c;parameterrealIS=1.0e-14;// User-configurable saturation currentrealidio;/* * Calculate nonlinear current through diode depending on * - thermal voltage $vt (at ambient temperature of simulated circuit) and * - voltage between terminals */analogbeginidio=IS*(limexp(V(a,c)/$vt)-1);I(a,c)<+idio;endendmoduleFor a simple DC voltage source, the branch voltage is set to the constant (DC) value:
// DC Sourcemodulevsrc(p,n);parameterrealdc=1.0;inoutp,n;electricalp,n;analogbegin// Assign constant DC voltage at each time step:V(p,n)<+dc;endendmoduleA sine voltage generator can use the built-in sin() function:
// A Sinusoidal Voltage Source`include"constants.vams"modulevsin(p,n);parameterrealamplitude=1.0;parameterrealfreq=50.0;parameterrealphase=0.0;inoutp,n;electricalp,n;analogbeginV(p,n)<+amplitude*sin(`M_TWO_PI*freq*$abstime+phase);$bound_step(0.1/freq);// demand at least 10 points per cycle to avoid aliasing issuesendendmodule
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