Constructing Hardware in a Scala Embedded Language (Chisel) | |
---|---|
![]() | |
Paradigms | Multi-paradigm: concurrent, functional, imperative, object-oriented |
Family | Scala |
Developer | University of California, Berkeley |
First appeared | June 2012 |
Stable release | 3.6.0 / April 14, 2023 |
Typing discipline | Inferred, static, strong, structural |
Scope | Lexical (static) |
Implementation language | Scala |
Platform | Java virtual machine (JVM) JavaScript (Scala.js) LLVM (Scala Native) (experimental) |
License | Apache License 2.0 |
Website | www |
Chisel (an acronym for Constructing Hardware in a Scala Embedded Language [1] ) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level. [2] [3]
Chisel is based on Scala as a domain-specific language (DSL). Chisel inherits the object-oriented and functional programming aspects of Scala for describing digital hardware. Using Scala as a basis allows describing circuit generators. High quality, free access documentation exists in several languages. [4]
Circuits described in Chisel can be converted to a description in Verilog for synthesis and simulation.
A simple example describing an adder circuit and showing the organization of components in Module with input and output ports:
classAddextendsModule{valio=IO(newBundle{vala=Input(UInt(8.W))valb=Input(UInt(8.W))valy=Output(UInt(8.W))})io.y:=io.a+io.b}
A 32-bit register with a reset value of 0:
valreg=RegInit(0.U(32.W))
A multiplexer is part of the Chisel library:
valresult=Mux(sel,a,b)
Although Chisel is not yet a mainstream hardware description language, it has been explored by several companies and institutions. The most prominent use of Chisel is an implementation of the RISC-V instruction set, the open-source Rocket chip. [5] Chisel is mentioned by the Defense Advanced Research Projects Agency (DARPA) as a technology to improve the efficiency of electronic design, where smaller design teams do larger designs. [6] Google has used Chisel to develop a Tensor Processing Unit for edge computing. [7] Some developers prefer Chisel as it requires one-fifth as much code and is much faster to develop than Verilog. [8]
Circuits described in Chisel can be converted to a description in Verilog for synthesis and simulation using a program named FIRRTL. [9] [ better source needed ]