MyHDL

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MyHDL [1] is a Python-based hardware description language (HDL).

Contents

Features of MyHDL include:

MyHDL is developed by Jan Decaluwe. [7]

Conversion examples

Here, you can see some examples of conversions from MyHDL designs to VHDL and/or Verilog. [8]

A small combinatorial design

The example is a small combinatorial design, more specifically the binary to Gray code converter:

defbin2gray(B,G,width:int):"""Gray encoder.    B -- input intbv signal, binary encoded    G -- output intbv signal, gray encoded    width -- bit width    """@always_combdeflogic():Bext=intbv(0)[width+1:]Bext[:]=Bforiinrange(width):G.next[i]=Bext[i+1]^Bext[i]returnlogic

You can create an instance and convert to Verilog and VHDL as follows:

width=8B=Signal(intbv(0)[width:])G=Signal(intbv(0)[width:])bin2gray_inst=toVerilog(bin2gray,B,G,width)bin2gray_inst=toVHDL(bin2gray,B,G,width)

The generated Verilog code looks as follows:

modulebin2gray(B,G);input[7:0]B;output[7:0]G;reg[7:0]G;always@(B)begin:BIN2GRAY_LOGICintegeri;reg[9-1:0]Bext;Bext=9'h0;Bext=B;for(i=0;i<8;i=i+1)beginG[i]<=(Bext[(i+1)]^Bext[i]);endendendmodule

The generated VHDL code looks as follows:

libraryIEEE;useIEEE.std_logic_1164.all;useIEEE.numeric_std.all;usestd.textio.all;usework.pck_myhdl_06.all;entitybin2grayisport(B:inunsigned(7downto0);G:outunsigned(7downto0));endentitybin2gray;architectureMyHDLofbin2grayisbeginBIN2GRAY_LOGIC:process(B)isvariableBext:unsigned(8downto0);beginBext:=to_unsigned(0,9);Bext:=resize(B,9);foriin0to8-1loopG(i)<=(Bext((i+1))xorBext(i));endloop;endprocessBIN2GRAY_LOGIC;endarchitectureMyHDL;

See also

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