Accellera

Last updated
Accellera
Formation2000 (2000)
Purpose Standards
Official language
English
Website accellera.org

Accellera Systems Initiative (Accellera) is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation (EDA) and integrated circuit (IC) design and manufacturing. It is less constrained than the Institute of Electrical and Electronics Engineers (IEEE) and is therefore the starting place for many standards. Once mature and adopted by the broader community, the standards are usually transferred to the IEEE. [1]

Contents

History

In 2000, Accellera was founded from the merger of Open Verilog International (OVI) and VHDL International, the developers of Verilog and VHDL respectively. Both were originally formed nine years earlier in 1991.

In June 2009, a merger was announced between Accellera and The SPIRIT Consortium, another major EDA standards organization focused on IP deployment and reuse. [2] The SPIRIT Consortium obtained SystemRDL from the SystemRDL Alliance [3] and then developed IP-XACT. The merger was completed in April 2010. [4] SPIRIT stood for "Structure for Packaging, Integrating and Re-using IP within Tool-flows".

In December 2011, Accellera and the Open SystemC Initiative (OSCI) approved their merger, adopting the name Accellera Systems Initiative (Accellera) while continuing to develop SystemC. [5] [6]

In October 2013, Accellera acquired the Open Core Protocol (OCP) standard, the intellectual property of the OCP International Partnership (OCP-IP). [7]

The SPIRIT Consortium

TheSPIRIT Consortium was a group of vendors and users of electronic design automation (EDA) tools, defining standards for the exchange of System-on-a-chip (SoC) design information. [8] The standards defined included IP-XACT, an XML schema for vendor-neutral descriptions of design components, and SystemRDL, a language for describing registers in components. [9] SPIRIT stood for "Structure for Packaging, Integrating and Re-using IP within Tool-flows".

In June 2009 it was announced that SPIRIT would merge with Accellera. [10]

SPIRIT membership

There were four levels of membership in the SPIRIT consortium. The Board of Directors (BoD) was the ruling body. [11] Members around the time of the merge were:

Contributing members performed the standardization work and donate time and effort to the production of new specifications. [12]

Reviewing member status was a free membership for companies. These get early access to specifications to facilitate a deep review round of each proposal before it goes public. [13]

Associate member status was similar to a reviewing membership but for academics and other not-for-profit organizations. [14]

Open Core Protocol International Partnership Association

The Open Core Protocol International Partnership Association, Inc. (OCP-IP) was an independent, non-profit semiconductor industry consortium formed to administer the support, promotion and enhancement of the Open Core Protocol (OCP). OCP was the first fully supported, openly licensed, comprehensive, interface socket for semiconductor intellectual property (IP) cores. The mission of OCP-IP was to address problems relating to design, verification, and testing which are common to IP core reuse in "plug and play" system on a chip (SoC) products. This initiative comprehensively fulfills system-level integration requirements by promoting IP core reusability and reducing design time, risk and manufacturing costs for SoC designs. Design teams developing consumer, data processing, telecom (wireless or wired), datacom and mass storage applications can gain significant benefits from the OCP-IP solution.

Accellera membership

Corporate members have a right to be eligible for election to the Board of Directors. Associate member companies have voting rights in all of Accellera's Technical Working Groups. [15]

Standards

The following EDA standards developed by Accellera were ratified by IEEE by 2019: [2]

The following EDA initiatives were developed by Accellera:

See also

Related Research Articles

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Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits. In 2009, the Verilog standard was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog has been officially part of the SystemVerilog language. The current version is IEEE standard 1800-2023.

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IP-XACT, also known as IEEE 1685, is an XML format that defines and describes individual, re-usable electronic circuit designs to facilitate their use in creating integrated circuits. IP-XACT was created by the SPIRIT Consortium as a standard to enable automated configuration and integration through tools and evolving into an IEEE standard.

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<span class="mw-page-title-main">Verilator</span>

Verilator is a free and open-source software tool which converts Verilog to a cycle-accurate behavioral model in C++ or SystemC. The generated models are cycle-accurate and 2-state; as a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can model behavior within the clock cycle. Verilator is now used within academic research, open source projects and for commercial semiconductor development. It is part of the growing body of free EDA software.

High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis, HLV is to HLS as functional verification is to logic synthesis.

The SystemRDL language, supported by the SPIRIT Consortium, was specifically designed to describe and implement a wide variety of control status registers. Using SystemRDL, developers can automatically generate and synchronize register views for specification, hardware design, software development, verification, and documentation.

References

  1. Accelera website
  2. 1 2 "EDA Standards Organizations Accellera and The SPIRIT Consortium Announce Plans to Merge".
  3. "SystemRDL Alliance".
  4. "Standards Organizations Accellera and The SPIRIT Consortium Complete Merger". 14 Apr 2010. Archived from the original on 18 May 2015. Retrieved 9 May 2015.
  5. "Accellera and Open SystemC Initiative (OSCI) Approve Merger, Unite to Form Accellera Systems Initiative".
  6. "Accellera and Open SystemC Initiative (OSCI) Approve Merger, Unite to Form Accellera Systems Initiative".
  7. "Accellera Systems Initiative Acquires Open Core Protocol Standard and Infrastructure to Strengthen Interoperability in Electronic Standards Development". 15 Oct 2013.
  8. Schemas of The SPIRIT Consortium
  9. Register description format gets 'Spirit' of standardization, Richard Goering, EE Times (05/21/2007 6:00 AM EDT)
  10. "EDA Standards Organizations Accellera and The SPIRIT Consortium Announce Plans to Merge", press release, Accellera. June 11, 2009
  11. Board of Directors
  12. Contributing Members
  13. Associate Members
  14. Reviewing Members
  15. Members