VHDL-VITAL

In computer chip design and manufacture VHDL-VITAL or simply VITAL, VHDL Initiative Towards ASIC Libraries, refers to the IEEE Standard 1076.4 Timing. ^[1]

References

1. "VHDL - VITAL". www.vhdl.renerta.com. Archived from the original on 2011-10-22.

• Krolikoski, S.J. (May 1995). "Standardizing ASIC libraries in VHDL using VITAL: a tutorial". Proceedings of the IEEE 1995 Custom Integrated Circuits Conference: 603–610. doi:10.1109/CICC.1995.518256.

• Vreeland, Russell E. "Connecting the System to the Chip: Using VHDL/VITAL for Board-level Simulation" (PDF). Retrieved 12 May 2025.

• Rushton, Andrew (2011). VHDL for logic synthesis (3rd ed.). Chichester, West Sussex, U.K: Wiley. p. 4. ISBN   9780470977972.

• Vreeland, Russell E. "Board-level component modeling using VITAL" . Retrieved 12 May 2025.

• Tuzov, Ilya; Ruiz, Juan-Carlos; de Andrés, David (September 2017). "Accurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level". 2017 13th European Dependable Computing Conference (EDCC). Institute of Electrical and Electronics Engineers: 10–17. doi:10.1109/EDCC.2017.26.