Registered memory (also called buffered memory) is computer memory that has a register between the DRAM modules and the system's memory controller. A registered memory module places less electrical load on a memory controller than an unregistered one. Registered memory allows a computer system to remain stable with more memory modules than it would have otherwise.
When conventional memory is compared with registered memory, conventional memory is usually referred to as unbuffered memory or unregistered memory. When registered memory is manufactured as a dual in-line memory module (DIMM), it is called an RDIMM. Similarly, an unregistered DIMM is called a UDIMM or simply "DIMM".
Registered memory is often more expensive because of the additional circuitry required and lower number of units sold, so it is usually found only in applications where the need for scalability and robustness outweighs the need for a low price – for example, registered memory is usually used in servers.
Although most registered memory modules also feature error-correcting code memory (ECC), it is also possible for registered memory modules to not be error-correcting or vice versa. Unregistered ECC memory is supported and used in workstation or entry-level server motherboards that do not support very large amounts of memory. [1]
Normally, there is a performance penalty for using registered memory. Each read or write is buffered for one cycle between the memory bus and the DRAM, so the registered RAM can be thought of as running one clock cycle behind the equivalent unregistered DRAM. With SDRAM, this only applies to the first cycle of a burst.
However, this performance penalty is not universal. There are many other factors involved in memory access speed. For example, the Intel Westmere 5600 series of processors access memory using interleaving, wherein memory access is distributed across three channels. If two memory DIMMs are used per channel, there is a reduction of maximum memory bandwidth for this configuration with UDIMM by some 5% in comparison to RDIMM. [2] [3]
Usually, the motherboard must match the memory type; as a result, registered memory will not work in a motherboard not designed for it, and vice versa. Some PC motherboards accept or require registered memory, but registered and unregistered memory modules cannot be mixed. [4] There is much confusion between registered and ECC memory; it is widely thought that ECC memory (which may or may not be registered) will not work at all in a motherboard without ECC support, not even without providing the ECC functionality, although the compatibility issues actually arise when trying to use registered memory (which often supports ECC and is described as ECC RAM) in a PC motherboard that does not support it.
Clocked Unbuffered DIMM (CUDIMM) modules include a buffer on the clock bus. [5]
Registered (Buffered) DIMM (R-DIMM or RDIMM) modules insert a buffer between the pins of the command and address buses (and the clock bus??) on the DIMM and the memory chips. A high-capacity DIMM might have numerous memory chips, each of which must receive the memory address, and their combined input capacitance limits the speed at which the memory bus can operate. By redistributing the command and address signals within the R-DIMM, this allows more chips to be connected to the memory bus. [7] The cost is increased memory latency, as a result of one[ citation needed ] additional clock cycle required for the address to traverse the additional buffer. Early registered RAM modules were physically incompatible with unregistered RAM modules, but the two variants of SDRAM R-DIMMs are mechanically interchangeable, and some motherboards may support both types. [8]
Load Reduced DIMM (LR-DIMM or LRDIMM) modules are similar to R-DIMMs, but add a buffer to the data lines as well. In other words, LR-DIMMs buffer both control and data lines while keeping the parallel nature of all signals. As a result, LR-DIMMs provide large overall maximum memory capacities, while avoiding the performance and power consumption problems of FB-DIMMs, induced by the required conversion between serial and parallel signal forms. [7] [9]
Fully Buffered DIMM (FB-DIMM) modules increase maximum memory capacities in large systems even more, using a more complex buffer chip to translate between the wide bus of standard SDRAM chips and a narrow, high-speed serial memory bus. In other words, all control, address and data transfers to FB-DIMMs are performed in a serial fashion, while the additional logic present on each FB-DIMM transforms serial inputs into parallel signals required to drive memory chips. [9] By reducing the number of pins required per memory bus, CPUs could support more memory buses, allowing higher total memory bandwidth and capacity. Unfortunately, the translation further increased memory latency, and the complex high-speed buffer chips used significant power and generated a lot of heat.
Both FB-DIMMs and LR-DIMMs are designed primarily to minimize the load that a memory module presents to the memory bus. They are not compatible with R-DIMMs, and motherboards that require them usually will not accept any other kind of memory modules.
Double Data Rate Synchronous Dynamic Random-Access Memory is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM and DDR5 SDRAM. None of its successors are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, DDR4 and DDR5 memory modules will not work on DDR1-equipped motherboards, and vice versa.
Dynamic random-access memory is a type of random-access semiconductor memory that stores each bit of data in a memory cell, usually consisting of a tiny capacitor and a transistor, both typically based on metal–oxide–semiconductor (MOS) technology. While most DRAM memory cell designs use a capacitor and transistor, some only use two transistors. In the designs where a capacitor is used, the capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The electric charge on the capacitors gradually leaks away; without intervention the data on the capacitor would soon be lost. To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory, since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.
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A Fully Buffered DIMM (FB-DIMM) is a type of memory module used in computer systems. It is designed to improve memory performance and capacity by allowing multiple memory modules to be each connected to the memory controller using a serial interface, rather than a parallel one. Unlike the parallel bus architecture of traditional DRAMs, an FB-DIMM has a serial interface between the memory controller and the advanced memory buffer (AMB). Conventionally, data lines from the memory controller have to be connected to data lines in every DRAM module, i.e. via multidrop buses. As the memory width increases together with the access speed, the signal degrades at the interface between the bus and the device. This limits the speed and memory density, so FB-DIMMs take a different approach to solve the problem.
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This results in a reduction of maximum memory bandwidth for 2DPC configurations with UDIMM by some 5% in comparison to RDIMM..
But when you go to 2 DIMMs per memory channel, due to the high electrical loading on the address and control lines, the memory controller use something called a "2T" or "2N" timing for UDIMMs.
Consequently every command that normally takes a single clock cycle is stretched to two clock cycles to allow for settling time. Therefore, for two or more DIMMs per channel, RDIMMs will have lower latency and better bandwidth than UDIMMs.