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LOCOS, short for LOCal Oxidation of Silicon, is a microfabrication process where silicon dioxide is formed in selected areas on a silicon wafer having the Si-SiO2 interface at a lower point than the rest of the silicon surface.
Microfabrication is the process of fabricating miniature structures of micrometre scales and smaller. Historically, the earliest microfabrication processes were used for integrated circuit fabrication, also known as "semiconductor manufacturing" or "semiconductor device fabrication". In the last two decades microelectromechanical systems (MEMS), microsystems, micromachines and their subfields, microfluidics/lab-on-a-chip, optical MEMS, RF MEMS, PowerMEMS, BioMEMS and their extension into nanoscale have re-used, adapted or extended microfabrication methods. Flat-panel displays and solar cells are also using similar techniques.
Silicon dioxide, also known as silica, silicic acid or silicic acid anhydride is an oxide of silicon with the chemical formula SiO2, most commonly found in nature as quartz and in various living organisms. In many parts of the world, silica is the major constituent of sand. Silica is one of the most complex and most abundant families of materials, existing as a compound of several minerals and as synthetic product. Notable examples include fused quartz, fumed silica, silica gel, and aerogels. It is used in structural materials, microelectronics (as an electrical insulator), and as components in the food and pharmaceutical industries.
This technology was developed to insulate MOS transistors from each other and limit transistor cross-talk. The main goal is to create a silicon oxide insulating structure that penetrates under the surface of the wafer, so that the Si-SiO2 interface occurs at a lower point than the rest of the silicon surface. This cannot be easily achieved by etching field oxide. Thermal oxidation of selected regions surrounding transistors is used instead. The oxygen penetrates in depth of the wafer, reacts with silicon and transforms it into silicon oxide. In this way, an immersed structure is formed. For process design and analysis purposes, the oxidation of silicon surfaces can be modeled effectively using the Deal–Grove model.
Silicon oxide may refer to either of the following:
In microfabrication, thermal oxidation is a way to produce a thin layer of oxide on the surface of a wafer. The technique forces an oxidizing agent to diffuse into the wafer at high temperature and react with it. The rate of oxide growth is often predicted by the Deal–Grove model. Thermal oxidation may be applied to different materials, but most commonly involves the oxidation of silicon substrates to produce silicon dioxide.
The Deal–Grove model mathematically describes the growth of an oxide layer on the surface of a material. In particular, it is used to predict and interpret thermal oxidation of silicon in semiconductor device fabrication. The model was first published in 1965 by Bruce Deal and Andrew Grove, of Fairchild Semiconductor.
Typical process steps are the following:
I. Preparation of silicon substrate (layer 1)
II. CVD of SiO2, pad/buffer oxide (layer 2)
III. CVD of Si3N4, nitride mask (layer 3)
IV. Etching of nitride layer (layer 3) and silicon oxide layer (layer 2)
V. Thermal growth of silicon oxide (structure 4)
VI. Further growth of thermal silicon oxide (structure 4)
VII. Removal of nitride mask (layer 3)
There are 4 basic layers/structures:
1-The silicon wafer (layer 1) is used as a basis for building electronic structures (such as MOS transistors).
To perform local oxidation, the areas not meant to be oxidized will be coated in a material that does not permit the diffusion of oxygen at high temperatures (thermal oxidation is performed in temperatures between 800 and 1200 °C), such as silicon nitride (layer 3, step III).
Diffusion is the net movement of molecules or atoms from a region of higher concentration to a region of lower concentration. Diffusion is driven by a gradient in chemical potential of the diffusing species.
Silicon nitride is a chemical compound of the elements silicon and nitrogen. Si
4 is the most thermodynamically stable of the silicon nitrides. Hence, Si
4 is the most commercially important of the silicon nitrides and is generally understood as what is being referred to where the term "silicon nitride" is used. It is a white, high-melting-point solid that is relatively chemically inert, being attacked by dilute HF and hot H
4. It is very hard. It has a high thermal stability.
During the growth of the immersed insulating thermal oxide structures (steps V and VI), the silicon nitride layer (layer 3) is pushed upwards. Without the buffer oxide (layer 2, also known as pad oxide), this would create too much tension in the Si substrate (layer 1), the plastic deformation would occur and the electronic devices would be damaged.
Therefore, a buffer oxide (layer 2) is deposed by the CVD (step II) between the Si substrate (layer 1) and the silicon nitride (layer 3). At high temperatures, the viscosity of silicon oxide decreases and the stress created between the silicon substrate (layer 1) and nitride layer (layer 3), by the growth of the thermal oxide (steps V and VI), is relieved.
Chemical vapor deposition (CVD) is a deposition method used to produce high quality, high-performance, solid materials, typically under vacuum. The process is often used in the semiconductor industry to produce thin films.
The insulating structures (structure 4) are formed by thermal oxidation of silicon. During this process, the silicon wafer is "consumed" and "replaced" by silicon oxide. The volume of silicon oxide to silicon is about 2.4:1, which explains the growth of the insulation structures and the created tension.
The disadvantage of this technology is that the insulating structures are rather large, and therefore, fewer MOS transistors can be formed on one wafer.
Reduction of dimensions of insulating structures is solved by the STI (Shallow Trench Isolation, also known as Box Isolation Technique). In this process, trenches are formed and silicon dioxide is deposed inside. The LOCOS technology can't be used in this way, because of the change of the volume during the thermal oxidation, which would induce too much stress in the trenches.
Microelectromechanical systems is the technology of microscopic devices, particularly those with moving parts. It merges at the nano-scale into nanoelectromechanical systems (NEMS) and nanotechnology. MEMS are also referred to as micromachines in Japan, or micro systems technology (MST) in Europe.
Semiconductor device fabrication is the process used to create the integrated circuits that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.
Gallium arsenide (GaAs) is a compound of the elements gallium and arsenic. It is a III-V direct bandgap semiconductor with a zinc blende crystal structure.
Epitaxy refers to the deposition of a crystalline overlayer on a crystalline substrate.
Silicon on insulator (SOI) technology refers to the use of a layered silicon–insulator–silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire. The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short channel effects in microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.
Tungsten(VI) fluoride, also known as tungsten hexafluoride, is an inorganic compound with the formula WF6. It is a toxic, corrosive, colorless gas, with a density of about 13 g/L (roughly 11 times heavier than air.) It is one of the densest known gases under standard conditions. WF6 is commonly used by the semiconductor industry to form tungsten films, through the process of chemical vapor deposition. This layer serves as a low-resistivity metallic "interconnect". It is one of seventeen known binary hexafluorides.
The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which modern integrated circuits are built. The process was developed by Jean Hoerni, one of the "traitorous eight", while working at Fairchild Semiconductor, with a first patent issued 1959.
Chemical mechanical polishing/planarization is a process of smoothing surfaces with the combination of chemical and mechanical forces. It can be thought of as a hybrid of chemical etching and free abrasive polishing.
An epitaxial wafer is a wafer of semiconducting material made by epitaxial growth (epitaxy) for use in photonics, microelectronics, spintronics, or photovoltaics. The epi layer may be the same material as the substrate, typically monocrystaline silicon, or it may be a more exotic material with specific desirable qualities.
Atomic layer deposition (ALD) is a thin-film deposition technique based on the sequential use of a gas phase chemical process; it is a subclass of chemical vapour deposition. The majority of ALD reactions use two chemicals called precursors. These precursors react with the surface of a material one at a time in a sequential, self-limiting, manner. Through the repeated exposure to separate precursors, a thin film is slowly deposited. ALD is a key process in the fabrication of semiconductor devices, and part of the set of tools available for the synthesis of nanomaterials.
Charge Trap Flash (CTF) is a semiconductor memory technology used in creating non-volatile NOR and NAND flash memory. The technology differs from the more conventional floating-gate MOSFET technology in that it uses a silicon nitride film to store electrons rather than the doped polycrystalline silicon typical of a floating gate structure. This approach allows memory manufacturers to reduce manufacturing costs five ways:
In electronics, a self-aligned gate is a transistor manufacturing feature whereby a refractory gate electrode region of a MOSFET transistor is used as a mask for the doping of the source and drain regions. This technique ensures that the gate will slightly overlap the edges of the source and drain.
A metal gate, in the context of a lateral Metal-Oxide-Semiconductor MOS stack, is just that—the gate material is made from a metal.
Lau Wai Shing, also known as Wai Shing Lau, is a Hong Kong electrical engineer and materials scientist. He worked on both Si-based and III-V based microelectronics.
A MIS capacitor is a capacitor formed from a layer of metal, a layer of insulating material and a layer of semiconductor material. It gets its name from the initials of the metal-insulator-semiconductor structure. As with the MOS field-effect transistor structure, for historical reasons, this layer is also often referred to as a MOS capacitor, but this specifically refers to an oxide insulator material.
Ultra-high-purity steam, also called clean steam, UHP steam or high purity water vapor, is used in a variety of industrial manufacturing processes that require oxidation or annealing. These processes include oxide layers grow on silicon wafers for the semiconductor industry and for passivation layers used to improve the light capture ability of crystalline photovoltaic cells. Several methods and technologies can be employed to generate ultra high purity steam, including pyrolysis, bubbling, direct liquid injection and purified steam generation. The level of purity, or the relative lack of contamination, affects the quality of the oxide layer or annealed surface. The method of delivery affects growth rate, uniformity and electrical performance. Oxidation and annealing are common steps in the manufacture of such devices as microelectronics and solar cells.
Eutectic bonding, also referred to as eutectic soldering, describes a wafer bonding technique with an intermediate metal layer that can produce a eutectic system. Those eutectic metals are alloys that transform directly from solid to liquid state, or vice versa from liquid to solid state, at a specific composition and temperature without passing a two-phase equilibrium, i.e. liquid and solid state. The fact that the eutectic temperature can be much lower than the melting temperature of the two or more pure elements can be important in eutectic bonding.
Two dimensional hexagonal boron nitride is a material of comparable structure to graphene with potential applications in e.g. photonics., fuel cells and as a substrate for two-dimensional heterostructures. 2D h-BN is isostructural to graphene, but where graphene is conductive, 2D h-BN is a wide-gap insulator.