Etch pit density

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The etch pit density (EPD) is a measure for the quality of semiconductor wafers. [1] [2]

Contents

Etching

An etch solution is applied on the surface of the wafer where the etch rate is increased at dislocations of the crystal resulting in pits. For GaAs one uses typically molten KOH at 450 degrees Celsius for about 40 minutes in a zirconium crucible. The density of the pits can be determined by optical contrast microscopy. Silicon wafers have usually a very low density of < 100 cm−2 while semi-insulating GaAs wafers have a density on the order of 105 cm−2.

Germanium detectors

High-purity Germanium detectors require the Ge crystals to be grown with a controlled range of dislocation density to reduce impurities. The etch pitch density requirement is typically within the range 103 to 104 cm−2.[ citation needed ]

Standards

The etch pit density can be determined according to DIN 50454-1 and ASTM F 1404. [3]

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The Wright etch is a preferential etch for revealing defects in <100>- and <111>-oriented, p- and n-type silicon wafers used for making transistors, microprocessors, memories, and other components. Revealing, identifying, and remedying such defects is essential for progress along the path predicted by Moore's Law. It was developed by Margaret Wright Jenkins (1936-2018) in 1976 while working in research and development at Motorola Inc. in Phoenix, AZ. It was published in 1977. This etchant reveals clearly defined oxidation-induced stacking faults, dislocations, swirls and striations with minimum surface roughness or extraneous pitting. These defects are known causes of shorts and current leakage in finished semiconductor devices should they fall across isolated junctions. A relatively low etch rate at room temperature provides etch control. The long shelf life of this etchant allows the solution to be stored in large quantities.

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References

  1. Zhuang, D.; Edgar, J.H. (2005). "Wet etching of GaN, AlN, and SiC: a review". Materials Science and Engineering: R: Reports. 48 (1): 1–46. doi:10.1016/j.mser.2004.11.002. ISSN   0927-796X.
  2. Klaus Graff (8 March 2013). Metal Impurities in Silicon-Device Fabrication. Springer Science & Business Media. pp. 152–. ISBN   978-3-642-97593-6.
  3. J. Doneker; I. Rechenberg (1 January 1998). Defect Recognition and Image Processing in Semiconductors 1997: Proceedings of the seventh conference on Defect Recognition and Image Processing, Berlin, September 1997. CRC Press. pp. 248–. ISBN   978-0-7503-0500-6.