Stephen Trimberger

Last updated
Stephen Trimberger
Born1955 (age 67–68)
Alma materCalifornia Institute of Technology (Ph.D.)
Known forField-Programmable Gate Array (FPGA) technology
AwardsNAE Member (2016)
IEEE Fellow
ACM Fellow
Scientific career
Fields Computer science

Stephen "Steve" Trimberger (born 1955) is an American computer scientist, electrical engineer, philanthropist, and prolific inventor with 250 US utility patents as of August 26, 2021. [1] He is a DARPA program manager of the microsystems technology office. [2]

Contents

Education

Trimberger grew up in Sacramento, California, and earned his B.S. in Engineering and Applied Science from the California Institute of Technology (Caltech), M.S. in Information and Computer Science from the University of California at Irvine, and Ph.D. in computer science from the California Institute of Technology.

While attending Caltech, Trimberger joined the Planet-Crossing Asteroid Survey (PCAS) project with principal investigator Gene Shoemaker, operated by Eleanor "Glo" Helin. PCAS searched for asteroids that could potentially impact planets, including Earth. In recognition of his contributions to this project, minor planet 2990 was named "Trimberger."

Career

Trimberger joined VLSI Technology in 1982, where, as a member of the original Design Technology group, he developed various computer-aided design software, including interactive tools, simulation, physical design automation, and logical design automation. During this time, he wrote An Introduction to CAD for VLSI, [3] collecting and explaining the fundamental algorithms and techniques used in the early days of the CAE industry.

Since 1988, he has been employed at Xilinx, a fabless semiconductor company in San Jose, California. He was a member of the architecture definition group for the Xilinx XC4000 field-programmable gate array (FPGA), the first FPGA with dedicated arithmetic and memory. [4] At the same time, he was the technical leader for the XC4000 design automation software. He led the architecture definition group for the Xilinx XC4000X device families. He developed a time-multiplexed FPGA [5] and software [6] to map to it in the 1990s, long before Tabula commercialized the time-folded FPGA. He is an inventor with approximately thirty patents in this area. In the early 1990s, he edited and co-wrote Field-Programmable Gate Array Technology, [7] introducing the first generation of academic researchers to the industrial side of programmable-logic architecture, tools and design.

He designed the bitstream security system for the Xilinx Virtex-II [US Patent #7,058,177], the first bitstream encryption deployed in FPGAs.[ citation needed ] His inventions on that security system are the basis of security in all commercial FPGAs from Xilinx and others.[ citation needed ] He was also instrumental in bringing 3D packaging from a lab curiosity to a product in the mid-2000s [US Patent 7,605,458]. This was deployed by Xilinx as Stacked Silicon Interconnect Technology (SSIT). [8] Trimberger led the Xilinx Advanced Development group for many years and is currently Xilinx Fellow in Xilinx Research Labs in San Jose.

Trimberger has written three books on computer-aided design for integrated circuits and FPGAs. He has written dozens of papers on design automation and FPGA architectures. [9] He is a four-time winner of the Ross Freeman Award, Xilinx’s annual award for technical innovation.[ citation needed ]

He was elected to the National Academy of Engineering in 2016 for his contributions to solid-state electronics.

Related Research Articles

<span class="mw-page-title-main">Field-programmable gate array</span> Array of logic gates that are reprogrammable

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools.

In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits.

<span class="mw-page-title-main">Application-specific integrated circuit</span> Integrated circuit customized for a specific task

An application-specific integrated circuit is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficiency video codec. Application-specific standard product chips are intermediate between ASICs and industry standard integrated circuits like the 7400 series or the 4000 series. ASIC chips are typically fabricated using metal–oxide–semiconductor (MOS) technology, as MOS integrated circuit chips.

Reconfigurable computing is a computer architecture combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computing fabrics like field-programmable gate arrays (FPGAs). The principal difference when compared to using ordinary microprocessors is the ability to make substantial changes to the datapath itself in addition to the control flow. On the other hand, the main difference from custom hardware, i.e. application-specific integrated circuits (ASICs) is the possibility to adapt the hardware during runtime by "loading" a new circuit on the reconfigurable fabric.

<span class="mw-page-title-main">Programmable Array Logic</span>

Programmable Array Logic (PAL) is a family of programmable logic device semiconductors used to implement logic functions in digital circuits introduced by Monolithic Memories, Inc. (MMI) in March 1978. MMI obtained a registered trademark on the term PAL for use in "Programmable Semiconductor Logic Circuits". The trademark is currently held by Lattice Semiconductor.

<span class="mw-page-title-main">Gate array</span> Type of integrated circuit

A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a prefabricated chip with components that are later interconnected into logic devices according to custom order by adding metal interconnect layers in the factory. It was popular during the upheaval in the semiconductor industry in the 1980s, and its usage declined by the end of the 1990s.

In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool. Common examples of this process include synthesis of designs specified in hardware description languages, including VHDL and Verilog. Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one step in circuit design in the electronic design automation, the others are place and route and verification and validation.

<span class="mw-page-title-main">Mixed-signal integrated circuit</span> Integrated circuit

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<span class="mw-page-title-main">Hardware acceleration</span> Specialized computer hardware

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Nallatech is a computer hardware and software firm based in Camarillo, California, United States. The company specializes in field-programmable gate array (FPGA) integrated circuit technology applied in computing. As of 2007 the company's primary markets include defense and high-performance computing. Nallatech was acquired by Interconnect Systems, Inc. in 2008, which in turn was bought by Molex in 2016.

A field-programmable analog array (FPAA) is an integrated circuit device containing computational analog blocks (CAB) and interconnects between these blocks offering field-programmability. Unlike their digital cousin, the FPGA, the devices tend to be more application driven than general purpose as they may be current mode or voltage mode devices. For voltage mode devices, each block usually contains an operational amplifier in combination with programmable configuration of passive components. The blocks can, for example, act as summers or integrators.

Jingsheng Jason Cong is a Chinese-born American computer scientist, educator, and serial entrepreneur. He received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. He has been on the faculty in the Computer Science Department at the University of California, Los Angeles (UCLA) since 1990. Currently, he is a Distinguished Chancellor’s Professor and the director of Center for Domain-Specific Computing (CDSC).

<span class="mw-page-title-main">Mark Horowitz</span> American electrical engineer (1957-)

Mark A. Horowitz is an American electrical engineer, computer scientist, inventor, and entrepreneur who is the Yahoo! Founders Professor in the School of Engineering and the Fortinet Founders Chair of the Department of Electrical Engineering at Stanford University. He holds a joint appointment in the Electrical Engineering and Computer Science departments and previously served as the Chair of the Electrical Engineering department from 2008 to 2012. He is a co-founder of Rambus Inc., now a technology licensing company. Horowitz has authored over 700 published conference and research papers and is among the most highly-cited computer architects of all time. He is a prolific inventor and holds 374 patents as of 2023.

High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior.

Computing with Memory refers to computing platforms where function response is stored in memory array, either one or two-dimensional, in the form of lookup tables (LUTs) and functions are evaluated by retrieving the values from the LUTs. These computing platforms can follow either a purely spatial computing model, as in field-programmable gate array (FPGA), or a temporal computing model, where a function is evaluated across multiple clock cycles. The latter approach aims at reducing the overhead of programmable interconnect in FPGA by folding interconnect resources inside a computing element. It uses dense two-dimensional memory arrays to store large multiple-input multiple-output LUTs. Computing with Memory differs from Computing in Memory or processor-in-memory (PIM) concepts, widely investigated in the context of integrating a processor and memory on the same chip to reduce memory latency and increase bandwidth. These architectures seek to reduce the distance the data travels between the processor and the memory. The Berkeley IRAM project is one notable contribution in the area of PIM architectures.

<span class="mw-page-title-main">Xilinx ISE</span> Hardware design tool

Xilinx ISE is a discontinued software tool from Xilinx for synthesis and analysis of HDL designs, which primarily targets development of embedded firmware for Xilinx FPGA and CPLD integrated circuit (IC) product families. It was succeeded by Xilinx Vivado. Use of the last released edition from October 2013 continues for in-system programming of legacy hardware designs containing older FPGAs and CPLDs otherwise orphaned by the replacement design tool, Vivado Design Suite.

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In computing, a logic block or configurable logic block (CLB) is a fundamental building block of field-programmable gate array (FPGA) technology. Logic blocks can be configured by the engineer to provide reconfigurable logic gates.

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Stephen Mathias Trimberger is an electrical engineer at Xilinx Inc. in San Jose, California. He was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2012 for his contributions to circuits, architectures and software technology for field-programmable gate arrays.

References

  1. ↑ Patents of Stephen M. Trimberger
  2. ↑ "Dr. Stephen Trimberger".
  3. ↑ Trimberger, Stephen (1987-06-30). An Introduction to CAD for VLSI. Springer. ISBN   0898382319.
  4. ↑ "FPL2012" . Retrieved 11 March 2014.
  5. ↑ Trimberger, S.; Carberry, D.; Johnson, A.; Wong, J. (1997). "A time-multiplexed FPGA". Time-Multiplexed FPGA. pp. 22–28. doi:10.1109/FPGA.1997.624601. ISBN   0-8186-8159-4. S2CID   2122414.
  6. ↑ Trimberger, Steve (1998). "Scheduling designs into a time-multiplexed FPGA". Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays - FPGA '98. pp. 153–160. doi:10.1145/275107.275135. ISBN   0897919785. S2CID   15857357 . Retrieved 11 March 2014.
  7. ↑ Trimberger, Stephen M.; Trimberger, Stephen (1994-01-31). Field-Programmable Gate Array Technology . Springer. ISBN   0792394194.
  8. ↑ "SEMI" . Retrieved 11 March 2014.
  9. ↑ "Stephen Trimberger". Association for Computing Machinery. Retrieved 26 May 2016.

[1] [2] [3] [4] [5]

  1. ↑ "2015 Hall of Fame Inductees | The Henry Samueli School of Engineering at UC Irvine". engineering.uci.edu. Retrieved 2018-03-10.
  2. ↑ "Stephen Trimberger". awards.acm.org. Retrieved 2018-03-10.
  3. ↑ "IEEE Fellows Made Their Mark on Industry - IEEE - The Institute". theinstitute.ieee.org. Retrieved 2018-03-10.
  4. ↑ Sengupta, A.; Frassetti, L. (Winter 2018). "William S. Carter and Stephen Trimberger Receive the 2018 IEEE Donald O. Pederson Award in Solid-State Circuits [IEEE News]". IEEE Solid-State Circuits Magazine. 10 (1): 82. doi:10.1109/MSSC.2017.2769470. ISSN   1943-0582.
  5. ↑ "Dr. Stephen M. Trimberger". NAE Website. Retrieved 2018-03-10.
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