AT&T Hobbit

Last updated

The AT&T Hobbit is a microprocessor design that AT&T Corporation developed in the early 1990s. It was based on the company's CRISP (C-language Reduced Instruction Set Processor) design resembling the classic RISC pipeline, and which in turn grew out of the C Machine design by Bell Labs of the late 1980s. All were optimized for running code compiled from the C programming language. The design concentrates on fast instruction decoding, indexed array access, and procedure calls.

Contents

The project was ended in March 1994 [1] because the Hobbit failed to achieve commercially viable sales.

History

The C Machine Project at Bell Labs had been underway since 1975 to develop computer architectures to run C programming language programs efficiently, aiming for a design that would offer an order of magnitude performance improvement over commercially available computers while remaining competitive in terms of cost. The design methodology for the C Machine architecture involved an iterative development approach informed by measurements of C program characteristics, involving the formulation and implementation of new computer architecture revisions, the development of a compiler to target each new revision, the compilation of "a large body of UNIX software", and the analysis of the compiled software. The results from such measurements then informed subsequent architecture revisions. [2]

Following on from the stabilization of the C Machine architecture in 1981 for an uncompleted ECL implementation, a design team was formed for CRISP in April 1983, and CRISP was first produced in a silicon implementation in 1986. The performance objectives were largely met by the fabricated processor, running at 16 MHz and delivering a Dhrystone benchmark score over 13 times greater than the VAX-11/750, achieving approximately 7.7 VAX MIPS. This was competitive with the MIPS R2000 as delivered in the MIPS M/500 Development System (an 8 MHz device delivering around 7.4 VAX MIPS [3] ) although some benchmarks showed somewhat stronger performance by the CRISP processor. Compared to the R2000 which required numerous support chips when incorporated into a computer system, the CRISP was a "complete" processor incorporating on-chip caches and had "substantially" reduced board area requirements. [2]

It was subsequently reoriented toward low-power applications and commercialized, resulting in the Hobbit. [4] It was introduced in 1992 in the form of the 92010 and aimed at the personal communicator market. Operating at 3.3V, its reported performance is up to 13.5 VAX MIPS. Initial pricing in multiples of 10,000 units was given as $35 per unit, with the full chipset below $100. [5] Several support chips were produced: [6]

AT&T followed in 1993 with the 92020 family of processors, introducing new support chipsets targeting different applications. These devices can run at 3.3V or at 5V with an elevated clock frequency. The 92020S is pin-compatible with the 92010, has a larger 6 KB instruction cache (as opposed to the 3 KB cache of the 92010 [7] ), and performs the equivalent of 16 VAX MIPS with a typical power consumption of 210 mW. [8] The 92020S was intended to be used in conjunction with most of the original 92010 chipset, excluding the 92013 peripheral controller. Meanwhile, the 92020M and 92020MX processors were intended for use with the new support chips, also employing a multiplexed address and data bus for reduced pin count, and offering lower levels of performance, with the 92020M also utilizing a 6 KB cache and achieving similar performance to the original 92010. The updated support chips are as follows: [7]

The most highly integrated processor, the 92020MX, preserved the 3 KB cache of the 92010 but has a single-channel PCMCIA interface and a display controller supporting resolutions of up to 640 x 480. Costing $32 per unit in 10,000 unit quantities, it presented opportunities for cost reduction with certain devices when compared to the original Hobbit chipset. [8]

Apple Computer approached AT&T and paid it to develop a newer version of the CRISP suitable for low-power use in the Newton handheld computer. The Hobbit-based Newton was never produced. According to Larry Tesler, "The Hobbit was rife with bugs, ill-suited for our purposes, and overpriced. We balked after AT&T demanded not one but several million more dollars in development fees." [9] Apple rejected the Hobbit and adopted the ARM610 for the Newton, [10] also partnering with Acorn Computers and VLSI Technology to form Advanced RISC Machines (ARM) in late 1990 with a $2.5 million investment. Apple sold its stake in ARM years later for a net $800 million. [9]

The Active Book Company (founded by Hermann Hauser, who also founded Acorn Computers), which had been using an ARM in its Active Book personal digital assistant (PDA), [11] was later purchased by AT&T and was subsumed by AT&T's Eo subsidiary, [12] which produced an early PDA, the EO Personal Communicator, running PenPoint OS from the GO Corporation. [13]

AT&T made early announcements in 1992 of broad vendor adoption. [14] Hobbit was used in the earliest prototypes of the BeBox until in 1993, AT&T announced discontinuation of Hobbit. [15] AT&T closed its Eo operations which were responsible for the only commercially released product using the Hobbit, [16] and finally discontinued the Hobbit in 1994. [17]

Design

In a traditional RISC design implementing a load–store architecture, memory is accessed through instructions that explicitly load data into registers and store data back to memory, with instructions that manipulate data working solely on the registers. By seeking to limit the data processing operations to a single clock cycle, a simpler control mechanism can be employed to dispatch instructions, making it easier to tune the instruction pipelines, [18] and add superscalar support. However, programming languages do not actually operate in this fashion. Generally they use a stack containing local variables and other information for subroutines known as a stack frame or activation record. The compiler writes code to create activation records using the underlying processor's load-store design.

The C Machine in its CRISP implementation, and the Hobbit that followed directly, both aim to support the types of memory access that programming languages use, with the C programming language being a particular consideration. [7] Instructions can access memory directly, referencing values in structures and arrays held within memory and updating memory with computation results. Although this memory-to-memory model is typical of the earlier CISC designs, the C Machine as implemented by CRISP differs from both CISC and RISC designs, including the earlier Bellmac 32, by providing no directly accessible registers. Instead, a "stack cache" of 32-bit register entries is provided, 32 entries in CRISP but extended to 64 entries in Hobbit, [19] :30 mapped to the address space corresponding to the top of the program stack, these being purely accessible using a stack-relative addressing mode. The CRISP architecture was described as a "2½ address memory-to-memory machine", where instructions can employ zero, one, or two memory addresses and can employ a stack entry called the accumulator for computation results. Reminiscent of the Bellmac 32 architecture, various instructions designed to support procedure calling are provided by the CRISP architecture: call saves the return address and branches to a routine; enter allocates a stack frame for a routine, flushing stack cache entries if necessary; return deallocates the stack frame and branches to the caller's return address; catch restores stack entries from memory. [2]

One side effect of the Hobbit design is that it inspired designers of the Dis virtual machine (an offshoot of Plan 9 from Bell Labs) to use a memory-to-memory-based system that more closely matches the internal register-based workings of real-world processors. They found, as RISC designers would have expected, that without a load-store design it was difficult to improve the instruction pipeline and thereby operate at higher speeds. They decided that all future processors would thus move to a load-store design, and built Inferno to reflect this. In contrast, Java and .NET virtual machines are stack-based, a side effect of being designed by language programmers as opposed to chip designers. Translating from a stack-based language to a register-based assembly language is a "heavyweight" operation; Java's virtual machine (VM) and compiler are many times larger and slower than the Dis VM and the Limbo (the most common language compiled for Dis) compiler. [20] The VMs for Android (Dalvik), Parrot, and Lua are also register-based.[ citation needed ]

See also

Related Research Articles

<span class="mw-page-title-main">DEC Alpha</span> 64-bit RISC instruction set architecture

Alpha is a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). Alpha was designed to replace 32-bit VAX complex instruction set computers (CISC) and to be a highly competitive RISC processor for Unix workstations and similar markets.

<span class="mw-page-title-main">Reduced instruction set computer</span> Processor executing one instruction in minimal clock cycles

In computer science, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler to achieve given simpler instructions.

<span class="mw-page-title-main">VAX</span> Line of computers sold by Digital Equipment Corporation

VAX is a series of computers featuring a 32-bit instruction set architecture (ISA) and virtual memory that was developed and sold by Digital Equipment Corporation (DEC) in the late 20th century. The VAX-11/780, introduced October 25, 1977, was the first of a range of popular and influential computers implementing the VAX ISA. The VAX family was a huge success for DEC, with the last members arriving in the early 1990s. The VAX was succeeded by the DEC Alpha, which included several features from VAX machines to make porting from the VAX easier.

The NS32000, sometimes known as the 32k, is a series of microprocessors produced by National Semiconductor. The first member of the family came to market in 1982, briefly known as the 16032 before becoming the 32016. It was the first general-purpose microprocessor on the market that used 32-bit data throughout: the Motorola 68000 used 32-bit data but had a 16-bit ALU and thus took twice as long perform many operations. However, the 32016 contained many bugs and often could not be run at its rated speed. These problems, and the presence of the otherwise similar 68000 which had been available since 1980, led to little use in the market.

In computer science, an instruction set architecture (ISA) is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an implementation.

The 88000 is a RISC instruction set architecture developed by Motorola during the 1980s. The MC88100 arrived on the market in 1988, some two years after the competing SPARC and MIPS. Due to the late start and extensive delays releasing the second-generation MC88110, the m88k achieved very limited success outside of the MVME platform and embedded controller environments. When Motorola joined the AIM alliance in 1991 to develop the PowerPC, further development of the 88000 ended.

Tandem Computers, Inc. was the dominant manufacturer of fault-tolerant computer systems for ATM networks, banks, stock exchanges, telephone switching centers, 911 systems, and other similar commercial transaction processing applications requiring maximum uptime and zero data loss. The company was founded by Jimmy Treybig in 1974 in Cupertino, California. It remained independent until 1997, when it became a server division within Compaq. It is now a server division within Hewlett Packard Enterprise, following Hewlett-Packard's acquisition of Compaq and the split of Hewlett-Packard into HP Inc. and Hewlett Packard Enterprise.

Alliant Computer Systems Corporation was a computer company that designed and manufactured parallel computing systems. Together with Pyramid Technology and Sequent Computer Systems, Alliant's machines pioneered the symmetric multiprocessing market. One of the more successful companies in the group, over 650 Alliant systems were produced over their lifetime. The company was hit by a series of financial problems and went bankrupt in 1992.

Pyramid Technology Corporation was a computer company that produced a number of RISC-based minicomputers at the upper end of the performance range. It was based in the San Francisco Bay Area of California

<span class="mw-page-title-main">Intel i960</span> RISC-based microprocessor design

Intel's i960 was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller. It became a best-selling CPU in that segment, along with the competing AMD 29000. In spite of its success, Intel stopped marketing the i960 in the late 1990s, as a result of a settlement with DEC whereby Intel received the rights to produce the StrongARM CPU. The processor continues to be used for a few military applications.

<span class="mw-page-title-main">DEC PRISM</span> RISC instruction set architecture

PRISM was a 32-bit RISC instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). It was the outcome of a number of DEC research projects from the 1982–1985 time-frame, and the project was subject to continually changing requirements and planned uses that delayed its introduction. This process eventually decided to use the design for a new line of Unix workstations. The arithmetic logic unit (ALU) of the microPrism version had completed design in April 1988 and samples were fabricated, but the design of other components like the floating point unit (FPU) and memory management unit (MMU) were still not complete in the summer when DEC management decided to cancel the project in favor of MIPS-based systems. An operating system codenamed MICA was developed for the PRISM architecture, which would have served as a replacement for both VAX/VMS and ULTRIX on PRISM.

In computer science, computer engineering and programming language implementations, a stack machine is a computer processor or a virtual machine in which the primary interaction is moving short-lived temporary values to and from a push down stack. In the case of a hardware processor, a hardware stack is used. The use of a stack significantly reduces the required number of processor registers. Stack machines extend push-down automata with additional load/store operations or multiple stacks and hence are Turing-complete.

<span class="mw-page-title-main">AMD Am29000</span> Family of RISC microprocessors and microcontrollers

The AMD Am29000, commonly shortened to 29k, is a family of 32-bit RISC microprocessors and microcontrollers developed and fabricated by Advanced Micro Devices (AMD). Based on the seminal Berkeley RISC, the 29k added a number of significant improvements. They were, for a time, the most popular RISC chips on the market, widely used in laser printers from a variety of manufacturers.

Berkeley RISC is one of two seminal research projects into reduced instruction set computer (RISC) based microprocessor design taking place under the Defense Advanced Research Projects Agency VLSI Project. RISC was led by David Patterson at the University of California, Berkeley between 1980 and 1984. The other project took place a short distance away at Stanford University under their MIPS effort starting in 1981 and running until 1984.

<span class="mw-page-title-main">Microarchitecture</span> Component of computer engineering

In electronics, computer science and computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. A given ISA may be implemented with different microarchitectures; implementations may vary due to different goals of a given design or due to shifts in technology.

<span class="mw-page-title-main">R4000</span> MIPS microprocessor

The R4000 is a microprocessor developed by MIPS Computer Systems that implements the MIPS III instruction set architecture (ISA). Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation. In the early 1990s, when RISC microprocessors were expected to replace CISC microprocessors such as the Intel i486, the R4000 was selected to be the microprocessor of the Advanced Computing Environment (ACE), an industry standard that intended to define a common RISC platform. ACE ultimately failed for a number of reasons, but the R4000 found success in the workstation and server markets.

<span class="mw-page-title-main">History of general-purpose CPUs</span> History of processors used in general purpose computers

The history of general-purpose CPUs is a continuation of the earlier history of computing hardware.

The R2000 is a 32-bit microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in January 1986, it was the first commercial implementation of the MIPS architecture and the first commercial RISC processor available to all companies. The R2000 competed with Digital Equipment Corporation (DEC) VAX minicomputers and with Motorola 68000 and Intel Corporation 80386 microprocessors. R2000 users included Ardent Computer, DEC, Silicon Graphics, Northern Telecom and MIPS's own Unix workstations.

RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. Many companies are offering or have announced RISC-V hardware; open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.

Since 1985, many processors implementing some version of the MIPS architecture have been designed and used widely.

References

  1. Dominic Giampaolo (2008). Practical File System Design.
  2. 1 2 3 Ditzel, David R.; McLellan, Hubert R.; Berenbaum, Alan D. (1987). "The hardware architecture of the CRISP microprocessor". Proceedings of the 14th annual international symposium on Computer architecture - ISCA '87. pp. 309–319. doi:10.1145/30350.30385. ISBN   0818607769. S2CID   14954824 . Retrieved March 28, 2023.
  3. Performance Brief Part 1: CPU Benchmarks (PDF) (Technical report). MIPS Computer Systems Inc. May 1988. p. 12. Retrieved September 28, 2021.
  4. Ryan, Bob (February 1993). "Communications Gets Personal". Byte. pp. 169–170, 172, 174, 176. Retrieved March 27, 2023.
  5. Booker, Ellis (November 2, 1992). "AT&T announces line of personal communicators". Computerworld. p. 41. Retrieved March 26, 2023.
  6. Cerda, Michael. "EO Block Diagram". Archived from the original on March 30, 2003. Retrieved May 15, 2009.
  7. 1 2 3 Statt, Paul (January 1994). "The AT&T Hobbit Enters Its Second Generation". Byte. p. 105. Retrieved March 26, 2023.
  8. 1 2 "AT&T Micro Unveils Fastest Hobbit MPU". Electronic News. October 18, 1993. p. 4. Retrieved March 26, 2023.
  9. 1 2 Tesler, Larry (April 11, 1999). "'The Fallen Apple' Corrections". Archived from the original on March 4, 2016. Retrieved August 21, 2020.
  10. Redfern, Andy (July 1992). "Apple ARMs Itself". Byte. p. 134. Retrieved October 10, 2022.
  11. "Xmas Launch for Active Books". Acorn User. August 1990. p. 7. Retrieved May 6, 2021.
  12. Kirkpatrick, David (May 17, 1993). "COULD AT&T RULE THE WORLD?". CNN. Retrieved June 10, 2008.
  13. Glitman, Russell (December 1992). "Eo Communicator: Lord of the Roads". PC World. p. 58. Retrieved March 30, 2023.
  14. "Wide hardware and applications support for AT&T Hobbit chips" (Press release). AT&T. November 16, 1992. Archived from the original on December 26, 1996. Retrieved March 30, 2023.
  15. Gassée, Jean-Louis (January 31, 2019). "50 Years In Tech Part 15. Be: From Concept To Near Death". Medium. Retrieved August 31, 2020.
  16. Smith, Ernie (January 3, 2020). "Fax on the beach: The story of the audacious, totally calamitous iPad of the '90s". Input. Retrieved November 1, 2020.
  17. Hacker, Scot; Bortman, Henry; Herborth, Chris (1999). The BeOS Bible. Peachpit Press. p. 34. ISBN   0201353776 . Retrieved March 30, 2023.
  18. Patterson, David A. (January 1985). "Reduced Instruction Set Computers". Communications of the ACM. Association for Computing Machinery. 28 (1): 8–21. doi: 10.1145/2465.214917 . S2CID   1493886 . Retrieved April 3, 2023.
  19. ATT92010 Hobbit Microprocessor. AT&T Microelectronics. December 1992. Retrieved April 7, 2023.
  20. "The design of the Inferno virtual machine". April 22, 2013. Archived from the original on April 22, 2013.