Motorola ECL 10,000 basic gate circuit diagram of 1972. Note how the Q5 and Q6 emitters coupled to the output.
In electronics, emitter-coupled logic (ECL) is a high-speed integrated circuit bipolar transistor logic family. ECL uses an overdriven bipolar junction transistor (BJT) differential amplifier with single-ended input and limited emitter current to avoid the saturated (fully on) region of operation and its slow turn-off behavior.[2] As the current is steered between two legs of an emitter-coupled pair, ECL is sometimes called current-steering logic (CSL),[3]current-mode logic (CML)[4] or current-switch emitter-follower (CSEF) logic.[5]
In ECL, the transistors are never in saturation, the input and output voltages have a small swing (0.8 V), the input impedance is high and the output impedance is low. As a result, the transistors change states quickly, gate delays are low, and the fanout capability is high.[6] In addition, the essentially constant current draw of the differential amplifiers minimises delays and glitches due to supply-line inductance and capacitance, and the complementary outputs decrease the propagation time of the whole circuit by reducing inverter count.
ECL's major disadvantage is that each gate continuously draws current, which means that it requires (and dissipates) significantly more power than those of other logic families, especially when quiescent.
A variation of ECL in which all signal paths and gate inputs are differential is known as differential current switch (DCS) logic.[8]
History
Yourke's current switch (around 1955)
ECL was invented in August 1956 at IBM by Hannon S. Yourke.[10][11] Originally called current-steering logic, it was used in the Stretch, IBM 7090, and IBM 7094 computers.[9] The logic was also called a current-mode circuit.[12] It was also used to make the ASLT circuits in the IBM 360/91.[13][14][15]
Yourke's current switch was a differential amplifier whose input logic levels were different from the output logic levels. "In current mode operation, however, the output signal consists of voltage levels which vary about a reference level different from the input reference level."[16] In Yourke's design, the two logic reference levels differed by 3volts. Consequently, two complementary versions were used: an NPN version and a PNP version. The NPN output could drive PNP inputs, and vice versa. "The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required."[9]
Instead of alternating NPN and PNP stages, another coupling method employed Zener diodes and resistors to shift the output logic levels to be the same as the input logic levels.[17]
Beginning in the early 1960s, ECL circuits were implemented on monolithic integrated circuits and consisted of a differential-amplifier input stage to perform logic and followed by an emitter-follower stage to drive outputs and shift the output voltages so they will be compatible with the inputs. The emitter-follower output stages could also be used to perform wired-or logic.
Motorola introduced their first digital monolithic integrated circuit line, MECL I, in 1962.[18] Motorola developed several improved series, with MECL II in 1966, MECL III in 1968 with 1-nanosecond gate propagation time and 300MHz flip-flop toggle rates, and the 10,000 series (with lower power consumption and controlled edge speeds) in 1971.[19] The MECL 10H family was introduced in 1981.[20] Fairchild introduced the F100K family.[when?]
The ECLinPS ("ECL in picoseconds") family was introduced in 1987.[21] ECLinPS has 500 ps single-gate delay and 1.1GHz flip-flop toggle frequency.[22] The ECLinPS family parts are available from multiple sources, including Arizona Microtek, Micrel, National Semiconductor, and ON Semiconductor.[23]
The high power consumption of ECL meant that it has been used mainly when high speed is a vital requirement. Older high-end mainframe computers, such as the Enterprise System/9000 members of IBM's ESA/390 computer family, used ECL,[24] as did the Cray-1;[25] and first-generation Amdahl mainframes. (Current IBM mainframes use CMOS.[26]) Beginning in 1975, Digital Equipment Corporation's highest performance processors were all based on multi-chip ECL CPUs—from the ECL KL10 through the ECL VAX 8000 and finally the VAX 9000. By 1991, the CMOS NVAX was launched which offered comparable performance to the VAX 9000 despite costing 25 times less and consuming considerably less power.[27] The MIPS R6000 computers also used ECL. Some of these computer designs used ECL gate arrays.
Implementation
The picture represents a typical ECL circuit diagram based on Motorola's MECL. In this schematic, transistor T5′ represents the output transistor of a previous ECL gate that provides a logic signal to input transistor T1 of an OR/NOR gate whose other input is at T2 and has outputs Y and Y. Additional pictures illustrate the circuit operation by visualizing the voltage relief and current topology at low input voltage (logical "0"), during the transition and at high input voltage (logical "1").
ECL is based on an emitter-coupled (long-tailed) pair, shaded red in the figure on the right. The left half of the pair (shaded yellow) consists of two parallel-connected input transistors T1 and T2 (an exemplary two-input gate is considered) implementing NOR logic. The base voltage of the right transistor T3 is held fixed by a reference voltage source, shaded light green: the voltage divider with a diode thermal compensation (R1, R2, D1 and D2) and sometimes a buffering emitter follower (not shown on the picture); thus the emitter voltages are kept relatively steady. As a result, the common emitter resistor RE acts nearly as a current source. The output voltages at the collector load resistors RC1 and RC3 are shifted and buffered to the inverting and non-inverting outputs by the emitter followers T4 and T5 (shaded blue). The output emitter resistors RE4 and RE5 do not exist in all versions of ECL. In some cases 50Ω line termination resistors connected between the bases of the input transistors and −2V act as emitter resistors.[28]
Operation
The ECL circuit operation is considered below with assumption that the input voltage is applied to T1 base, while T2 input is unused or a logical "0" is applied.
During the transition, the core of the circuit – the emitter-coupled pair (T1 and T3) – acts as a differential amplifier with single-ended input. The "long-tail" current source (RE) sets the total current flowing through the two legs of the pair. The input voltage controls the current flowing through the transistors by sharing it between the two legs, steering it all to one side when not near the switching point. The gain is higher than at the end states (see below) and the circuit switches quickly.
At low input voltage (logical "0") or at high input voltage (logical "1") the differential amplifier is overdriven. The transistor (T1 or T3) is cutoff and the other (T3 or T1) is in active linear region acting as a common-emitter stage with emitter degeneration that takes all the current, starving the other cutoff transistor. The active transistor is loaded with the relatively high emitter resistance RE that introduces a significant negative feedback (emitter degeneration). To prevent saturation of the active transistor so that the diffusion time that slows the recovery from saturation will not be involved in the logic delay,[2] the emitter and collector resistances are chosen such that at maximum input voltage some voltage is left across the transistor. The residual gain is low (K=RC/RE<1). The circuit is insensitive to the input voltage variations and the transistor stays firmly in active linear region. The input resistance is high because of the series negative feedback. The cutoff transistor breaks the connection between its input and output. As a result, its input voltage does not affect the output voltage. The input resistance is high again since the base-emitter junction is cutoff.
Characteristics
Other noteworthy characteristics of the ECL family include the fact that the large current requirement is approximately constant, and does not depend significantly on the state of the circuit. This means that ECL circuits generate relatively little power noise, unlike other logic types which draw more current when switching than quiescent. In cryptographic applications, ECL circuits are also less susceptible to side channel attacks such as differential power analysis.[citation needed]
The propagation time for this arrangement can be less than a nanosecond, including the signal delay getting on and off the IC package. Some type of ECL has always been the fastest logic family.[29][30]
Radiation hardening: While normal commercial-grade chips can withstand 100 gray (10 krad), many ECL devices are operational after 100,000 gray (10 Mrad).[31]
Power supplies and logic levels
ECL circuits usually operate with negative power supplies (positive end of the supply is connected to ground). Other logic families ground the negative end of the power supply. This is done mainly to minimize the influence of the power supply variations on the logic levels. ECL is more sensitive to noise on the VCC and is relatively immune to noise on VEE.[32] Because ground should be the most stable voltage in a system, ECL is specified with a positive ground. In this connection, when the supply voltage varies, the voltage drops across the collector resistors change slightly (in the case of emitter constant current source, they do not change at all). As the collector resistors are firmly "tied up" to ground, the output voltages "move" slightly (or not at all). If the negative end of the power supply was grounded, the collector resistors would be attached to the positive rail. As the constant voltage drops across the collector resistors change slightly (or not at all), the output voltages follow the supply voltage variations and the two circuit parts act as constant current level shifters. In this case, the voltage divider R1-R2 compensates the voltage variations to some extent. The positive power supply has another disadvantage — the output voltages will vary slightly (±0.4 V) against the background of high constant voltage (+3.9 V). Another reason for using a negative power supply is protection of the output transistors from an accidental short circuit developing between output and ground[33] (but the outputs are not protected from a short circuit with the negative rail).
The value of the supply voltage is chosen so that sufficient current flows through the compensating diodes D1 and D2 and the voltage drop across the common emitter resistor RE is adequate.
ECL circuits available on the open market usually operated with logic levels incompatible with other families. This meant that interoperation between ECL and other logic families, such as the popular TTL family, required additional interface circuits. The fact that the high and low logic levels are relatively close meant that ECL suffers from small noise margins, which can be troublesome.
At least one manufacturer, IBM, made ECL circuits for use in the manufacturer's own products. The power supplies were substantially different from those used in the open market.[24]
PECL
Positive emitter-coupled logic, also called pseudo-ECL, (PECL) is a further development of ECL using a positive 5V supply instead of a negative 5.2V supply.[34] Low-voltage positive emitter-coupled logic (LVPECL) is a power-optimized version of PECL, using a positive 3.3V instead of 5V supply. PECL and LVPECL are differential-signaling systems and are mainly used in high-speed and clock-distribution circuits.
A common misconception is that PECL devices are slightly different from ECL devices. In fact, every ECL device is also a PECL device.[35]
An amplifier, electronic amplifier or (informally) amp is an electronic device that can increase the magnitude of a signal. It is a two-port electronic circuit that uses electric power from a power supply to increase the amplitude of a signal applied to its input terminals, producing a proportionally greater amplitude signal at its output. The amount of amplification provided by an amplifier is measured by its gain: the ratio of output voltage, current, or power to input. An amplifier is defined as a circuit that has a power gain greater than one.
An operational amplifier is a DC-coupled electronic voltage amplifier with a differential input, a (usually) single-ended output, and an extremely high gain. Its name comes from its original use of performing mathematical operations in analog computers.
In electronics, a comparator is a device that compares two voltages or currents and outputs a digital signal indicating which is larger. It has two analog input terminals and and one binary digital output . The output is ideally
Transistor–transistor logic (TTL) is a logic family built from bipolar junction transistors. Its name signifies that transistors perform both the logic function and the amplifying function, as opposed to earlier resistor–transistor logic (RTL) and diode–transistor logic (DTL).
NMOS or nMOS logic uses n-type (-) MOSFETs to implement logic gates and other digital circuits.
In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. It outputs a bit opposite of the bit that is put into it. The bits are typically implemented as two differing voltage levels.
In electronics, a multi-transistor configuration called the Darlington configuration is a circuit consisting of two bipolar transistors with the emitter of one transistor connected to the base of the other, such that the current amplified by the first transistor is amplified further by the second one. The collectors of both transistors are connected together. This configuration has a much higher current gain than each transistor taken separately. It acts like and is often packaged as a single transistor. It was invented in 1953 by Sidney Darlington.
A differential amplifier is a type of electronic amplifier that amplifies the difference between two input voltages but suppresses any voltage common to the two inputs. It is an analog circuit with two inputs and and one output , in which the output is ideally proportional to the difference between the two voltages:
In electronics, a Schmitt trigger is a comparator circuit with hysteresis implemented by applying positive feedback to the noninverting input of a comparator or differential amplifier. It is an active circuit which converts an analog input signal to a digital output signal. The circuit is named a trigger because the output retains its value until the input changes sufficiently to trigger a change. In the non-inverting configuration, when the input is higher than a chosen threshold, the output is high. When the input is below a different (lower) chosen threshold the output is low, and when the input is between the two levels the output retains its value. This dual threshold action is called hysteresis and implies that the Schmitt trigger possesses memory and can act as a bistable multivibrator. There is a close relation between the two kinds of circuits: a Schmitt trigger can be converted into a latch and a latch can be converted into a Schmitt trigger.
Resistor–transistor logic (RTL), sometimes also known as transistor–resistor logic (TRL), is a class of digital circuits built using resistors as the input network and bipolar junction transistors (BJTs) as switching devices. RTL is the earliest class of transistorized digital logic circuit; it was succeeded by diode–transistor logic (DTL) and transistor–transistor logic (TTL).
Diode–transistor logic (DTL) is a class of digital circuits that is the direct ancestor of transistor–transistor logic. It is called so because the logic gating functions AND and OR are performed by diode logic, while logical inversion (NOT) and amplification is performed by a transistor.
In computer engineering, a logic family is one of two related concepts:
IC power-supply pins denote a voltage and current supply terminals in electric, electronics engineering, and in integrated circuit design. Integrated circuits (ICs) have at least two pins that connect to the power rails of the circuit in which they are installed. These are known as the power-supply pins. However, the labeling of the pins varies by IC family and manufacturer. The double subscript notation usually corresponds to a first letter in a given IC family (transistors) notation of the terminals.
Current mode logic (CML), or source-coupled logic (SCL), is a digital design style used both for logic gates and for board-level digital signaling of digital data.
Integrated injection logic (IIL, I2L, or I2L) is a class of digital circuits built with multiple collector bipolar junction transistors (BJT). When introduced it had speed comparable to TTL yet was almost as low power as CMOS, making it ideal for use in VLSI (and larger) integrated circuits. The gates can be made smaller with this logic family than with CMOS because complementary transistors are not needed. Although the logic voltage levels are very close (High: 0.7V, Low: 0.2V), I2L has high noise immunity because it operates by current instead of voltage. I2L was developed in 1971 by Siegfried K. Wiedmann and Horst H. Berger who originally called it merged-transistor logic (MTL). A disadvantage of this logic family is that the gates draw power when not switching unlike with CMOS.
Open collector, open drain, open emitter, and open source refer to integrated circuit (IC) output pin configurations that process the IC's internal function through a transistor with an exposed terminal that is internally unconnected. One of the IC's internal high or low voltage rails typically connects to another terminal of that transistor. When the transistor is off, the output is internally disconnected from any internal power rail, a state called "high-impedance" (Hi-Z). Open outputs configurations thus differ from push–pull outputs, which use a pair of transistors to output a specific voltage or current.
Direct-coupled transistor logic (DCTL) is similar to resistor–transistor logic (RTL) but the input transistor bases are connected directly to the collector outputs without any base resistors. Consequently, DCTL gates have fewer components, are more economical, and are simpler to fabricate onto integrated circuits than RTL gates. Unfortunately, DCTL has much smaller signal levels, has more susceptibility to ground noise, and requires matched transistor characteristics. The transistors are also heavily overdriven; that is a good feature in that it reduces the saturation voltage of the output transistors, but it also slows the circuit down due to a high stored charge in the base. Gate fan-out is limited due to "current hogging": if the transistor base-emitter voltages are not well matched, then the base-emitter junction of one transistor may conduct most of the input drive current at such a low base-emitter voltage that other input transistors fail to turn on.
Baker clamp is a generic name for a class of electronic circuits that reduce the storage time of a switching bipolar junction transistor (BJT) by applying a nonlinear negative feedback through various kinds of diodes. The reason for slow turn-off times of saturated BJTs is the stored charge in the base. It must be removed before the transistor will turn off since the storage time is a limiting factor of using bipolar transistors and IGBTs in fast switching applications. The diode-based Baker clamps prevent the transistor from saturating and thereby accumulating a lot of stored charge.
High-threshold logic (HTL), also known as low-speed logic (LSL) or high-level logic (HLL), is a variant of diode–transistor logic used in environments where noise is very high.
The diamond buffer or diamond follower is a four-transistor, two-stage, push-pull, translinear emitter follower, or less commonly source follower, in which the input transistors are folded, or placed upside-down with respect to the output transistors. Like any unity buffer, the diamond buffer does not alter the phase and magnitude of input voltage signal; its primary purpose is to interface a high-impedance voltage source with a low-impedance, high-current load. Unlike the more common compound emitter follower, where each input transistor drives the output transistor of the same polarity, each input transistor of a diamond buffer drives the output transistor of the opposite polarity. When the transistors operate in close thermal contact, the input transistors stabilize the idle current of the output pair, eliminating the need for a bias spreader.
References
↑ Original drawing based on Blood Jr., William R. (1972). MECL System Design Handbook(PDF) (2nded.). Motorola Semiconductor Products. p.1 – via Bitsavers.
↑ Blood Jr., William R. (1988) [1980]. MECL System Design Handbook(PDF) (4thed.). Motorola Semiconductor Products, republished by On Semiconductor. p.vi. Archived from the original(PDF) on October 10, 2004.
↑ Blood Jr., William R. (October 1971). MECL System Design Handbook(PDF) (1sted.). Motorola. pp.vi–vii – via Bitsavers.
↑ Supnik, Bob. "Raven: Introduction: The ECL Conundrum". Raven was started in 1988... Raven was a simplified VAX design with a single chip CPU and a single chip FPU. Implemented in Fujitsu's ECL standard cells, it was intended to run at 250Mhz and deliver 50 "VUPS" ... Power dissipation would have been a startling (for the day) 150W.
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