Cycle stealing

Last updated

In computing, traditionally cycle stealing is a method of accessing computer memory (RAM) or bus without interfering with the CPU. It is similar to direct memory access (DMA) for allowing I/O controllers to read or write RAM without CPU intervention. Clever exploitation of specific CPU or bus timings can permit the CPU to run at full speed without any delay if external devices access memory not actively participating in the CPU's current activity and complete the operations before any possible CPU conflict.

Contents

Cycle stealing was common in older platforms, first on supercomputers which used complex systems to time their memory access, and later on early microcomputers where cycle stealing was used both for peripherals as well as display drivers. It is more difficult to implement in modern platforms because there are often several layers of memory running at different speeds, and access is often mediated by the memory management unit. In the cases where the functionality is needed, modern systems often use dual-port RAM which allows access by two systems, but this tends to be expensive.

In older references, the term is also used to describe traditional DMA systems where the CPU stops during memory transfers. In this case the device is stealing cycles from the CPU, so it is the opposite sense of the more modern usage.

Common implementations

Some processors were designed to allow cycle stealing, or at least supported it easily. This was the case for the Motorola 6800 and MOS 6502 systems due to a design feature which meant the CPU only accessed memory every other clock cycle. Using RAM that was running twice as fast as the CPU clock allowed a second system to interleave its accesses between the CPUs by timing themselves on every other clock cycle. This was widely used for updating the display using main memory as a framebuffer. Common RAM of the late 1970s ran at 2 MHz, so most machines had a CPU running around 1 MHz. The BBC Micro secured a supply of 4 MHz RAM which allowed its CPU to run at 2 MHz.

Another common solution was to use separate banks of memory that stored instructions vs. data, or more than one pool of data. In these cases the I/O systems can access their data memory while the processor is using a different bank. One example is the Zilog Z80, whose M1 line indicates that the processor is reading instructions; if those instructions are in a different bank, or more commonly ROM, the I/O systems can access RAM without interfering with the processor.

Modern architecture

Cycle stealing is difficult to achieve in modern systems due to many factors such as pipelining, where pre-fetch and concurrent elements are constantly accessing memory, leaving few predictable idle times to sneak in memory access. DMA is the only formal and predictable method for external devices to access RAM.

This term is less common in modern computer architecture (above 66-100 MHz), where the various external buses and controllers generally run at different rates, and CPU internal operations are no longer closely coupled to I/O bus operations.

Examples in actual computer systems

Unexpected cycle stealing by the rendezvous radar during descent nearly caused the Apollo 11 landing to be aborted, but the design of the Guidance Computer allowed the landing to continue by dropping low-priority tasks.

The IBM 1130's "cycle steal" is really DMA because the CPU clock is stopped during memory access. Several I/O controllers access RAM this way. They self-arbitrate via a fixed priority scheme. Most controllers deliberately pace RAM access to minimize impact on the system's ability to run instructions, but others, such as graphic video adapters, operate at higher speed and may slow down the system.

The cycle-stealing concept of the 1130 permits the CPU program to start an operation on an I/O device and then continue the mainline program while the I/O device is performing its operation. Each I/O device that operates in this manner takes (steals) a cycle from the CPU when it is needed.

The CPU is "tied up" only one cycle while a data character is being transferred. The frequency at which devices steal cycles depends on the type of device.

Since the CPU is much faster than any I/O device on the system, the CPU may be performing another function, such as arithmetic, at the same time an I/O operation is being performed. In fact, several I/O operations may be overlapped with each other and with other CPU functions. [1]

Cycle stealing has been the cause of major performance degradation on machine such as the Sinclair QL, where, for economy reasons, the video RAM was not dual access. Consequently, the M68008 CPU was denied access to the memory bus when the ZX8301 "master controller" was accessing memory, and the machine performed poorly when compared with machines using similar processors at similar speeds.

Related Research Articles

<span class="mw-page-title-main">Bus (computing)</span> System that transfers data between components within a computer

In computer architecture, a bus is a communication system that transfers data between components inside a computer, or between computers. This expression covers all related hardware components and software, including communication protocols.

<span class="mw-page-title-main">Intel 8086</span> 16-bit microprocessor

The 8086 is a 16-bit microprocessor chip designed by Intel between early 1976 and June 8, 1978, when it was released. The Intel 8088, released July 1, 1979, is a slightly modified chip with an external 8-bit data bus, and is notable as the processor used in the original IBM PC design.

Direct memory access (DMA) is a feature of computer systems and allows certain hardware subsystems to access main system memory independently of the central processing unit (CPU).

Chip RAM is a commonly used term for the integrated RAM used in Commodore's line of Amiga computers. Chip RAM is shared between the central processing unit (CPU) and the Amiga's dedicated chipset. It was also, rather misleadingly, known as "graphics RAM".

<span class="mw-page-title-main">Transputer</span> Series of pioneering microprocessors from the 1980s

The transputer is a series of pioneering microprocessors from the 1980s, intended for parallel computing. To support this, each transputer had its own integrated memory and serial communication links to exchange data with other transputers. They were designed and produced by Inmos, a semiconductor company based in Bristol, United Kingdom.

<span class="mw-page-title-main">Intel 8085</span> 8-bit microprocessor by Intel

The Intel 8085 ("eighty-eighty-five") is an 8-bit microprocessor produced by Intel and introduced in March 1976. It is software-binary compatible with the more-famous Intel 8080 with only two minor instructions added to support its added interrupt and serial input/output features. However, it requires less support circuitry, allowing simpler and less expensive microcomputer systems to be built.

<span class="mw-page-title-main">Intel 4040</span> 4-bit microprocessor introduced in 1974 by Intel

The Intel 4040 microprocessor was the successor to the Intel 4004. It was introduced in 1974. The 4040 employed a 10 μm silicon gate enhancement load PMOS technology, was made up of 3,000 transistors and could execute approximately 62,000 instructions per second. General performance, bus layout and instruction set was identical to the 4004, with the main improvements being in the addition of extra lines and instructions to recognise and service interrupts and hardware Halt/Stop commands, an extended internal stack and general-purpose "Index" register space to handle nesting of several subroutines and/or interrupts, plus a doubling of program ROM address range.

<span class="mw-page-title-main">Front-side bus</span> Type of computer communication interface

A front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the central processing unit (CPU) and a memory controller hub, known as the northbridge.

<span class="mw-page-title-main">TI MSP430</span>

The MSP430 is a mixed-signal microcontroller family from Texas Instruments, first introduced on 14 February 1992. Built around a 16-bit CPU, the MSP430 is designed for low cost and, specifically, low power consumption embedded applications.

Memory-mapped I/O (MMIO) and port-mapped I/O (PMIO) are two complementary methods of performing input/output (I/O) between the central processing unit (CPU) and peripheral devices in a computer. An alternative approach is using dedicated I/O processors, commonly known as channels on mainframe computers, which execute their own instructions.

<span class="mw-page-title-main">Atari Falcon</span> Personal computer

The Atari Falcon030, released in 1992, was the final personal computer product from Atari Corporation. A high-end model of the Atari ST line, the machine is based on a Motorola 68030 CPU and a Motorola 56001 digital signal processor, a feature which distinguishes it from most other microcomputers of the era. It includes a new VIDEL programmable graphics system which greatly improves graphics capabilities.

<span class="mw-page-title-main">Zilog Z280</span>

The Zilog Z280 is a 16-bit microprocessor, an enhancement of the Zilog Z80 architecture, introduced in July 1987. It is basically the Z800, renamed, with slight improvements such as being fabricated in CMOS. It was a commercial failure. Zilog added a memory management unit (MMU) to expand the addressing range to 16 MB, features for multitasking and multiprocessor and coprocessor configurations, and 256 bytes of on-chip static RAM, configurable as either a cache for instructions and/or data, or as part of the ordinary address space. It has a huge number of new instructions and addressing modes giving a total of over 2000 combinations. It is capable of efficiently handling 32-bit data operations including hardware multiply, divide, and sign extension. It offers Supervisor and User operating modes, and optionally separate address spaces for instructions and data in both modes. Its internal clock signal can be configured to run at 1, 2 or 4 times the external clock's speed. Unlike the Z80 the Z280 uses a multiplexed arrangement for its address and data busses. More successful extensions of the Z80-architecture include the Hitachi HD64180 in 1986 and Zilog eZ80 in 2001, among others. See further Zilog Z800.

<span class="mw-page-title-main">Blackfin</span>

The Blackfin is a family of 16-/32-bit microprocessors developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point digital signal processor (DSP) functionality supplied by 16-bit multiply–accumulates (MACs), accompanied on-chip by a microcontroller. It was designed for a unified low-power processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding.

<span class="mw-page-title-main">Signetics 2650</span> 8-bit microprocessor

The Signetics 2650 was an 8-bit microprocessor introduced in July 1975. According to Adam Osborne's book An Introduction to Microprocessors Vol 2: Some Real Products, it was "the most minicomputer-like" of the microprocessors available at the time. A combination of missing features and odd memory access limited its appeal, and the system saw little use in the market.

<span class="mw-page-title-main">Low Pin Count</span> Low-bandwidth computer motherboard bus

The Low Pin Count (LPC) bus is a computer bus used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the BIOS ROM, "legacy" I/O devices, and Trusted Platform Module (TPM). "Legacy" I/O devices usually include serial and parallel ports, PS/2 keyboard, PS/2 mouse, and floppy disk controller.

In computing, channel I/O is a high-performance input/output (I/O) architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computers. In the past, channels were generally implemented with custom devices, variously named channel, I/O processor, I/O controller, I/O synchronizer, or DMA controller.

<span class="mw-page-title-main">Ricoh 5A22</span> Microprocessor made by Ricoh for the Super Nintendo Entertainment System

The Ricoh 5A22 is an 8/16-bit microprocessor produced by Ricoh for the Super Nintendo Entertainment System (SNES) video game console. It is based on the 8/16-bit WDC 65C816, which was developed between 1982 and 1984 for the Apple IIGS personal computer. It has 92 instructions, an 8-bit data bus, a 16-bit accumulator, and a 24-bit address bus. The CPU runs between 1.79 MHz and 3.58 MHz, and uses an extended MOS Technology 6502 instruction set.

<span class="mw-page-title-main">CPU multiplier</span>

In computing, the clock multiplier sets the ratio of an internal CPU clock rate to the externally supplied clock. A CPU with a 10x multiplier will thus see 10 internal cycles for every external clock cycle. For example, a system with an external clock of 100 MHz and a 36x clock multiplier will have an internal CPU clock of 3.6 GHz. The external address and data buses of the CPU also use the external clock as a fundamental timing base; however, they could also employ a (small) multiple of this base frequency to transfer data faster.

<span class="mw-page-title-main">General Instrument CP1600</span>

The CP1600 is a 16-bit microprocessor created in a partnership between General Instrument and Honeywell in 1975. It was among the first single-chip 16-bit processors; only the Texas Instruments TMS9900 is close in introduction date. The overall design bore a strong resemblance to the PDP-11.

<span class="mw-page-title-main">Intel 8237</span>

Intel 8237 is a direct memory access (DMA) controller, a part of the MCS 85 microprocessor family. It enables data transfer between memory and the I/O with reduced load on the system's main processor by providing the memory with control signals and memory address information during the DMA transfer.

References

  1. IBM 1130 Cycle-Stealing Concept