Ferranti F100-L

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The Ferranti F100-L was a 16-bit microprocessor family announced by Ferranti in 1976 which entered production in 1977. It was the first microprocessor designed in Europe, [1] and among the first 16-bit single-chip CPUs. It was designed with military use in mind, able to work in a very wide temperature range and radiation hardened. To deliver these capabilities, the F100 was implemented using bipolar junction transistors, as opposed to the metal oxide semiconductor (MOS) process used by most other processors of the era. The family included a variety of support chips including a multiply/divide unit, various memory support chips, timers and serial bus controllers.

Contents

The F100 was priced at £39 in 1978 in 100-off quantities. Three models were offered at the same price; the commercial spec was rated at 8 MHz, industrial at 6.5 MHz at an extended temperature range, and military spec at 3.5 or 5 MHz with a temperature range from -55 C to +125 C. It was very cost competitive in the industrial and military markets, but less so in the commercial market where processors like the MOS 6502 were about $11 in the same 100 unit quantity.

The line was updated with the F200-L in 1984. This was software compatible with the F100, but included the maths processor on the same die, expanded addressing to 128 kB, and allowed up to 1 MB of memory when paired with the new F220 memory management unit. Shortly after the F200 came to market, in 1987 Ferranti purchased International Signal and Control, a company soon discovered to be committing large amounts of fraud; this drove Ferranti into bankruptcy.

The chip division was purchased by Plessey who continued producing some of the F100 family support chips as late as 1995. Owing to it being used almost entirely in the military realm, the F100 is little known in the wider retrocomputing field and few examples remain.

History

Previous computers

Ferranti was among the first companies to introduce a commercial computer, the Ferranti Mark 1 of 1951. They followed this with several other commercial designs, most notably the Ferranti Atlas of 1962, for a time the fastest computer in the world. In 1963 they used the Ferranti-Packard 6000, developed independently at their Canadian division, as the "golden brick" in the sale of their entire commercial computing line to International Computers and Tabulators (ICT). ICT used the FP6000 as the basis for their 1900 line, which sold for years. Prior to the sale, Ferranti sold about 24% of all computing hardware in the UK. [2]

As part of the deal with ICT, Ferranti were barred from sales into the commercial computer market. This left them with two existing architectures that had been developed for military uses, the small Ferranti Argus that had already become a success in the industrial controller market, and the FM 1600, a larger machine used for realtime data handling, weapons control and simulation. [3] Both were built of individual transistors and small scale integration integrated circuits using Ferranti's MicroNor bipolar transistor process. These were both very successful in the market, generating hundreds of millions of pounds of sales through the late 1960s. [2]

CDI

A significant problem with the MicroNor process was that a logic gate implemented using bipolar layout was significantly larger than one using the contemporary MOSFET process, about six times. [lower-alpha 1] In typical designs, the bipolar layout also required three or four extra masking steps, each of which was time-consuming and increased the possibility of the chip being damaged during processing. Experience with MicroNor suggested that a maximum of about 100 gates was the limit for a single chip, in contrast to MOS, which was being used for designs with thousands of gates. However, the MOS system was more sensitive to impurities in the semiconductor feedstock, which led to electrical noise that reduced performance and also limited its operating conditions. Neither was acceptable in the military market. [1]

In 1971, Ferranti licensed the new collector-diffusion-isolation (CDI) process from Fairchild Semiconductor. This process, originally developed at Bell Labs, produced a dramatically simplified bipolar gate which required fewer masking steps and was only slightly larger than the equivalent MOS. This was of little interest to either Bell or Fairchild, who were happy with their MOS processes, and neither had progressed beyond experimental systems. [1]

Ferranti invested heavily in the CDI process, working to raise the operating voltage from 3 to 5V for compatibility with their existing transistor-transistor logic (TTL) devices that were already widely used in military applications. [4] This led to a series of medium scale integration parts using the process. Most well known among these was a series of uncommitted logic arrays (ULA, or gate array), chips with no pre-set logic design that could be programmed by the developer to produce any required circuit. These became very popular, and by 1986 the company held about 20% of the worldwide market for ULAs. [4]

F100-L

The introduction of the first microprocessors in the early 1970s cut into Ferranti's military computing business. While these early designs were not competitive in performance terms, their price/performance ratio was orders of magnitude better than Ferranti's discrete designs, in spite of several rounds of cost-reduction in the MicroNor line in the late 1960s. Convinced that the microprocessor represented a strategic change in military applications, in 1974 the UK Ministry of Defence agreed to sponsor an effort by Ferranti to produce a military-grade microprocessor design using the CDI process, whose high power-handling allowed them to operate in electrically noisy environments. [2]

An internal survey within the company suggested that an 8-bit part would not have the capability needed by the various divisions, and the decision was made to produce a 16-bit part. [1] Based on studies of the economics of chip fabrication, Ferranti concluded that they had a budget of about 1,000 gates before the design would be too expensive. To produce a 16-bit design with this limited gate count, the arithmetic logic unit (ALU) used a bit-serial architecture. This slows the performance of mathematical operations, so that the minimum time needed to complete an instruction is 36 clock cycles. This performance hit is offset somewhat by the 8 MHz clock speed, roughly double that of the fastest CPUs of the era. [5]

With 16-bit data and 15-bit addresses, normally 31 pins would be required to interface the design to the computer as a whole. Desiring a low-cost solution, it had to fit into a conventional 40-pin dual in-line package (DIP). To accomplish this, the data and address lines share pins, and thus require multiple cycles to complete the reading of a single instruction. [4] For comparison, the Texas Instruments TMS9900, another 16-bit design introduced the same year, had double the gate count and was packaged in an expensive custom 64-pin DIP. [5]

Ultimately the F100 failed to meet its 1,000 gate limitation and was built with about 1,500 gates on a 5.8 mm square surface. This was larger than their existing mask-production system and required them to develop a new version with a larger optical reduction ratio. The timing of the design effort also produced one advantage; the F100 was beginning to be readied for production just as the Micralign system was coming to market, and Ferranti adopted this projection alignment system for production, thereby greatly improving yields. [6]

As was common at the time, the F100 was introduced along with a family of support chips, including memory bus interfaces, interrupt controller, a direct memory access controller and a basic serial bus controller. Most of these were built using their ULA chips. [7] Perhaps most interesting among these was the F101-L, released shortly after the CPU, which performed hardware multiplication and division. This became so common that the CPU was soon offered with the F101 on the same die, as the FBH5092. [7]

While the F100 was being developed, Ferranti produced a multi-card rackmount version of the CPU, the F100-M. This was used as a development platform and saw some civilian use as well. Programming tools were initially written in FORTRAN, but most projects were written in CORAL once a compiler for that language became available. [8]

When it was first announced in 1977, 100-unit lots were priced at £57, but that was soon reduced to £39 by 1978. [4] A set containing an F100 along with the F111-L control interface and two F112-L DMA controllers was available for an additional £18. [6] While this made it uncompetitive with MOS-based commercial processors like the $25 Zilog Z80 or $11 MOS 6502 in the same 100-unit lots, it was very competitive with other military-spec designs like the Z80's military-rated unit at $165. [9]

The F100 quickly found use in UK defense projects. Among the more well-known successes was the guidance unit for the Sea Eagle missile. Other examples include the gunnery computer for the Falcon self-propelled anti-aircraft gun, a variety of ballistics computers used in various tanks, the CPU for the UoSAT-1 satellite, and a number of naval computer applications. [8] It was also used in the civilian field in engine management systems from Ultra Electronic Controls, a propeller speed limiter from Dowty Group, and even control of nuclear test equipment using the CAMAC protocol. [9]

F200-L

The F100 line was updated in 1984 with the introduction of the F200-L, which was software and pin-compatible with the F100. The primary changes were to include the math processor, formerly the F101, as part of the base CPU. Improvements in fabrication also allowed the F200-L to run up to 20 MHz. The F200 also supported the 16th bit in addresses, expanding the memory to 64 kW (128 kB). The new F220-L memory management unit, launched at the same time, provided address lookup within a 1 MW (2 MB) memory space. [7]

Plessey purchase

During the 1980s, Ferranti was very successful and cash-flush. Desiring to make more sales into the United States, the company began looking for an established US military supplier they could buy and use as the basis for their own division in the country. This process eventually led them to purchase International Signal and Control (ISC) in 1987, and along with it, changing the name of the company to Ferranti International. [10]

Unfortunately, ISC's major business, unrevealed at the time, was illegal arms sales. This source of income evaporated with the purchase, leaving them with practically no ongoing business. A lengthy court process ensued, and the debt load of the purchase along with the cost of the litigation drove Ferranti into bankruptcy in December 1993. [10]

As part of the bankruptcy proceedings, the company was broken up, and the semiconductor division was purchased by Plessey. This was subsequently part of the Siemens Plessey unit after Siemens purchased the company in 1989. The line continued to be produced through this period, with the F100/200 itself being produced until at least 1992, [9] and some of the other members until 1995. [11]

Today

Used primarily in military systems, few F100 systems remain today. Among the few are a display F100-L chip at the Museum of Science and Industry in Manchester, also there are two types of display F100-L chips and a DATA book at The ICL Computer Museum, and a small number of cards from a F100 microcomputer at the Centre for Computing History. [9]

Description

Registers

Most microprocessors of the 1970s used internal 8-bit wide processor registers, an 8-bit data bus and a 16-bit address bus. The F100 used 16-bit registers but only 15-bits in the address bus, but these addresses represented 16-bit words so the total addressable memory was 64 kB, as was the case with most 8-bit processors with 16-bit addressing. [6] At the time the F100 was designed, memory was extremely expensive and typical machines of the era generally featured only 4 kB of SRAM, so the missing 16th bit in the address was not an important consideration. [9]

There are three main user registers. The 16-bit ACC (accumulator) and OR (operand register) are used to hold values being manipulated by the arithmetic logic unit (ALU) during calculations and comparisons. The results of these operations set bits in the 7-bit CR (condition register). Two additional registers are used internally; the 15-bit PC (program counter) holds the address of the currently executing instruction and has an auto-increment feature, while the 16-bit IR (instruction register) is used to hold the actual instruction itself. If the instruction operates on a memory address, the value in the IR is moved to internal latches and the IR is then loaded with the address value. [9]

The CR contained a set of seven bits: [9]

! BitMnemonicNameFunction
0IInterrupt Disabledisables interrupts when set
1ZZerotrue if the last comparison resulted in zero
2VoVerflowtrue if the last operation overflowed the ACC
3NNegativetrue if the last operation resulted in a negative
4CCarrytrue if the last math or shift requires a carry
5MMulti-Lengthwhen true, the C bit will be added to math operations and shifts
6FFailtrue if the last external operation timed out

Addressing modes

The F100 had a total of four addressing modes; direct, immediate, pointer and immediate indirect. [7]

Direct mode encoded a constant value directly into the instruction. To do this, only the upper five bits were available for the opcode, allowing a total of 32 possible direct instructions, while the remaining lower 11 bits stored the numeric value. [7] In the standard assembler mnemonics, this was indicated by placing the value directly after the instruction. For instance, AND 0x444 would perform a bitwise AND operation between the current value in the ACC and the 16-bit constant 0x444. Immediate mode was similar to direct, but the value to be accessed is placed in the 16-bits following the instruction in order to allow larger constants. This was indicated with a comma, for instance, AND ,0x4444. [9]

As was common at the time, the F100 featured a form of zero page addressing they referred to as Pointer Indirect Addressing, or simply pointer. Address zero, a 16-bit word, was used as the stack pointer, which lacked its own register. This had to be set to an odd number. Locations 1 through 255 were available for the user. Pointer addressing used the lower 8 bits of the instruction to indicate one of the zero page addresses, whose value would be read as an address, and then the value at that address would be loaded. [7] Pointer addressing was indicated with a slash, for instance, AND /0x44. [9]

Additionally, the F100 had alternate forms of the pointer addressing instructions that performed a pre-increment or post-decrement of the value in the pointer in the zero page. These make it easy to perform loops over blocks of data in main memory without needing a separate increment operation to be read and performed. [7] These were indicated using the + or - at the end of the pointer value, for instance, AND /0x44+ or AND /0x44-. [9]

Finally, indirect addressing was similar to pointer addressing but allows any value in memory to hold the pointer, rather than just the zero page. [7] This is more flexible, but as the address is stored in the 16 bits following the instruction, using this method is slower than zero page because two memory addresses have to be read instead of one. This mode was specified with a dot, for instance, AND .0x4444. [9]

Some of the indirect addressing mode instructions also took a third value, indicating another location in memory. This was used for bitwise comparisons; the instructions included which bit to be tested as the first operand, the location in memory as the second, and the address to jump to as the third. [7] For instance, JBS 0x2 0x4444 0x5555 would test the second bit of the value in location 0x4444 and then jump to location 0x5555 if it was set, or continue on if it was not. [9]

Because the addressing format in the instructions varied in length, memory was naturally broken into segments. The first was the stack pointer in location zero, next was the remaining 255 locations of the zero page, then the maximum 2048 locations of the direct mode (which included the zero page), and finally the remaining memory which could be accessed by the 15-bit addresses. [9]

Instructions

The F100 had a total of 29 instructions, which combined using the various addressing modes results in 153 opcodes. The instructions generally fall into six main categories; math and logical, double-length (32-bit) math and logical, bit tests and conditional branches, interrupt handling, and external functions. The later allows unused bits of the instruction to be passed to external chips for processing. [6]

The instructions were relatively common but had some variations. For instance, ADD and SUB had alternate versions, ADS and SBS, which performed the operation and then stored the result back into the operand address. JMP performed an unconditional jump, while CAL called a subroutine, what most assemblers would call a JSR, and RTN performed a return. Conditional branches allowed test-and-jump. [7]

The instruction format used various fields to encode instructions classes. The four most significant bits, 15 through 12, selected the actual instruction, for instance, 1001 was ADD. The rest of the bits varied depending on the addressing mode. For instance, if direct addressing was being used, bit 11 was set to 0, 10 and 9 to 1, and the remaining 11 bits encoded the address of the operand. If the 11 bits were all set to zero, it instead read the operand from the next 16 bits in memory. [9]

Start up

On startup or reset, the processor examines the AdSel pin (address select). If the pin voltage represents a zero, it jumps to location 0x4000, or 16384 decimal, while if the pin is 1, it jumps to 0x0800, 2048. By placing startup code in ROM at those locations, the boot process can be automated. [9]

Notes

  1. ↑ See diagrams, Evans p. 21. [4]

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References

Citations

  1. 1 2 3 4 Push 1977, p. 448.
  2. 1 2 3 Evans & Spittles 2019, p. 20.
  3. ↑ "A history of automated AIO's" (PDF). Royal Navy. Archived from the original (PDF) on 18 October 2012.
  4. 1 2 3 4 5 Evans & Spittles 2019, p. 21.
  5. 1 2 Evans & Spittles 2019, pp. 21–22.
  6. 1 2 3 4 Push 1977, p. 449.
  7. 1 2 3 4 5 6 7 8 9 10 Evans & Spittles 2019, p. 22.
  8. 1 2 Evans & Spittles 2019, p. 23.
  9. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Evans 2016.
  10. 1 2 "The ISC / Ferranti Scandal". Archived from the original on 17 December 2017. Retrieved 13 December 2008.
  11. ↑ Evans & Spittles 2019, p. 25.

Bibliography

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