Field-effect tetrode

A field-effect tetrode is a four-terminal field-effect semiconductor device. The term was introduced in 1959 for a class of dual-channel field-effect devices. It was later reused during the 1960s for certain multi-gate MOS devices used primarily in radio-frequency electronics.

Symmetric channel structure

The tetrode field-effect transistor ^[1] or field-effect tetrode is a solid-state semiconductor device, constructed by creating two independently contacted field-effect channels separated by a junction. In this form, it is a four-terminal device which does not have specific gate terminals because each channel acts as a gate for the other, ^[2] the voltage conditions modulating the current carried by the other channel. ^[3]

The device was analyzed by H. A. Stone Jr. and R. M. Warner Jr. of Bell Laboratories in a 1961 paper. ^[4] The authors described a symmetrical structure of adjacent n-type and p-type conduction channels sharing a reverse-biased junction, with two terminals connected to each channel. The current in each channel depends on all four terminal voltages. The paper developed current–voltage relationships based on this mutual control and discussed applications including electronically variable resistors, impedance inversion, nonreciprocal signal transmission, and voltage-controlled negative resistance.

Current–voltage relationship

The current–voltage behavior of the device can be expressed analytically by modeling the n-type and p-type channels as two conduction paths whose currents are jointly determined by all four terminal voltages.

Where the voltage on the first channel is ${\displaystyle V_{1}-V_{2}}$ and the voltage on the second channel is ${\displaystyle V_{3}-V_{4}}$, the current in the first channel, ${\displaystyle I_{1}}$, and the current in the second channel, ${\displaystyle I_{2}}$, are given by:

${\displaystyle I_{1}=G_{1}(V_{1}-V_{2})\left[1-{\frac {2}{3V_{p}^{1/2}}}{\frac {(V_{1}-V_{3})^{(3/2)}-(V_{2}-V_{4})^{(3/2)}}{(V_{1}-V_{3})-(V_{2}-V_{4})}}\right]}$

and

${\displaystyle I_{2}=G_{2}(V_{3}-V_{4})\left[1-{\frac {2}{3V_{p}^{1/2}}}{\frac {(V_{3}-V_{1})^{(3/2)}-(V_{4}-V_{2})^{(3/2)}}{(V_{3}-V_{1})-(V_{4}-V_{2})}}\right]}$,

where the ${\displaystyle G_{i}}$ are the low-voltage conductance of the channels and ${\displaystyle V_{p}}$ is the pinch-off voltage (assumed to be the same for each channel).

Applications

The field-effect tetrode can be used as a highly linear electronically variable resistor – resistance is not modulated by signal voltage. Signal voltage can exceed bias voltage, pinch-off voltage, and junction breakdown voltage. The limit is dependent on dissipation. Signal current flows in inverse proportion to the channel resistances. The signal does not modulate the depletion layer, so the tetrode can perform at high frequencies. The tuning ratio can be very large – the high resistance limit is in the megohms range for symmetrical pinch-off conditions. ^[2]

MOS tetrodes and dual-gate MOSFETs

In radio-frequency electronics, the term MOS tetrode has been used to describe dual-gate MOSFETs, in which two separate gate electrodes control a single conduction channel. These devices were developed for RF amplifier applications, where one gate is used for signal input and the other for gain control, reducing feedback in a manner analogous to a screen grid. Their multi-gate structure provides good dynamic range and improved high-frequency performance, and they are often analyzed as cascode stages to explain their behavior at VHF frequencies. ^{[5] [6] [7]}

See also

• Field-effect transistor
• Multigate device, other multi-gate devices
• Tetrode transistor, any transistor having four active terminals

References

1. Tetrode field-effect transistor Archived 8 December 2015 at the Wayback Machine , JEDEC definition
2. Raymond M. Warner Jr.; James N. Fordemwalt, eds. (1965). Integrated Circuits: Design Principles and Fabrication. McGraw Hill. pp. 220–223.
3. Christopher G. Morris, ed. (15 September 1992). Academic Press Dictionary of Science and Technology . Academic Press. p.  824. ISBN   9780122004001.
4. Stone, H. A.; Warner, R. M. (July 1961). "The Field-Effect Tetrode". Proceedings of the IRE. 49 (7): 1170–1183.
5. Ditrick, N.; Mitchell, M.; Dawson, R. (1965). "A low-power MOS tetrode". International Electron Devices Meeting. Washington, DC, US: IEEE. p. 62. doi:10.1109/IEDM.1965.187628.
6. Burns, Joseph (September 1967). "High-Frequency Characteristics of the Insulated-Gate Field-Effect Transistor". RCA Review. 28 (3): 396–400.
7. Okumura, T. (January 1969). "The MOS tetrode". Philips Technical Review. 30 (1): 134–141.