SciEngines GmbH

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SciEngines GmbH is a privately owned company founded 2007 as a spin-off of the COPACOBANA [1] project by the Universities of Bochum and Kiel, both in Germany. The project intended to create a platform for an affordable Custom hardware attack. COPACOBANA [2] is a massively-parallel reconfigurable computer. It can be utilized to perform a so-called Brute force attack to recover DES [3] [4] encrypted data. It consists of 120 commercially available, reconfigurable integrated circuits (FPGAs). These Xilinx Spartan3-1000 run in parallel, and create a massively parallel system. Since 2007, SciEngines GmbH has enhanced and developed successors of COPACOBANA. Furthermore, the COPACOBANA has become a well known reference platform for cryptanalysis and custom hardware based attacks to symmetric, asymmetric cyphers and stream ciphers. 2008 attacks against A5/1 stream cipher an encryption system been used to encrypt voice streams in GSM have been published as the first known real world attack utilizing off-the-shelf custom hardware. [5] [6]

They introduced in 2008 their RIVYERA S3-5000 [7] enhancing the performance of the computer dramatically via using 128 Spartan-3 5000's. Currently SciEngines RIVYERA holds the record in brute-force breaking DES utilizing 128 Spartan-3 5000 FPGAs. [8] Current systems provide a unique density of up to 256 Spartan-6 FPGAs per single system enabling scientific utilization beyond the field of cryptanalysis, like bioinformatics. [9]

2006 original developers of the COPACOBANA [10] form the company
2007 introduction of the COPACOBANA (Copacobana S3-1000) as a [COTS]
2007 first demonstration of COPACOBANA 5000 [11]
2008 they introduced RIVYERA S3-5000, the direct successor of COPACOBANA 5000 and COPACOBANA. The RIVYERA architecture introduced a new high performance optimized bus system and a fully API encapsulated communication framework.
2008 demonstration of the COPACOBANA V4-SX35, a 128 Virtex-4 SX35 FPGA cluster (COPACOBANA shared bus architecture)
2008 introduction of the RIVYERA V4-SX35, a 128 Virtex-4 SX35 FPGA cluster (RIVYERA HPC architecture)
2009 they introduced RIVYERA S6-LX150.
2011 they introduced 256 User usable FPGAs per RIVYERA S6-LX150 computer.


Providing a standard off-the-shelf Intel CPU and mainboard integrated into the FPGA computer RIVYERA [12] systems allow to execute most standard code without modifications. SciEngines aims that programmers only have to focus on porting the most time-consuming 5% of their code to the FPGA. Therefore, they bundle an Eclipse like development environment which allows code implementation in hardware based implementation languages e.g. VHDL, Verilog as well as in C based languages. An Application Programming Interface in C, C++, Java and Fortran allow scientists and programmers to adopt their code to benefit from an application-specific hardware architecture.

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References

  1. ↑ "COPACOBANA Project".
  2. ↑ "COPACOBANA : FPGA based DES Cracker". 2009-08-16.
  3. ↑ "SHARCS Workshop, April 3.- 4., 2006, Cologne, How to Break DES for € 8,980" (PDF).
  4. ↑ "COPACOBANA in german computer magazine c't".
  5. ↑ "A Real-World Attack Breaking A5/1 within Hours" (PDF).
  6. ↑ "Hardware-Based Cryptanalysis of the GSM A5/1 Encryption Algorithm" (PDF).
  7. ↑ "RIVYERA from SciEngines".
  8. ↑ "Break DES in less than a single day" (Press release). Demonstrated at 2009 Workshop.
  9. ↑ Forster, Michael; Szymczak, Silke; Ellinghaus, David; Hemmrich, Georg; Rühlemann, Malte; Kraemer, Lars; Mucha, Sören; Wienbrandt, Lars; Stanulla, Martin; Franke, Andre; Franke, A. (2015). "Vy-PER: eliminating false positive detection of virus integration events in next generation sequencing data". Scientific Reports. 5: 11534. Bibcode:2015NatSR...511534.. doi:10.1038/srep11534. PMC   4499804 . PMID   26166306.
  10. ↑ "COPACOBANA : FPGA based DES Cracker". 2009-08-16.
  11. ↑ "RIVYERA from SciEngines" (PDF).
  12. ↑ "HOCHLEISTUNGSCLUSTER RIVYER".

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