Microvias are used as the interconnects between layers in high density interconnect (HDI) substrates and printed circuit boards (PCBs) to accommodate the high input/output (I/O) density of advanced packages. Driven by portability and wireless communications, the electronics industry strives to produce affordable, light, and reliable products with increased functionality. At the electronic component level, this translates to components with increased I/Os with smaller footprint areas (e.g. flip-chip packages, chip-scale packages, and direct chip attachments), and on the printed circuit board and package substrate level, to the use of high density interconnects (HDIs) (e.g. finer lines and spaces, and smaller vias).
A printed circuit board (PCB) mechanically supports and electrically connects electronic components or electrical components using conductive tracks, pads and other features etched from one or more sheet layers of copper laminated onto and/or between sheet layers of a non-conductive substrate. Components are generally soldered onto the PCB to both electrically connect and mechanically fasten them to it.
In computing, input/output or I/O is the communication between an information processing system, such as a computer, and the outside world, possibly a human or another information processing system. Inputs are the signals or data received by the system and outputs are the signals or data sent from it. The term can also be used as part of an action; to "perform I/O" is to perform an input or output operation.
A via or VIA is an electrical connection between layers in a physical electronic circuit that goes through the plane of one or more adjacent layers. To ensure via robustness, IPC sponsored a round-robin exercise that developed a time to failure calculator.
IPC standards revised the definition of a microvia in 2013 to a hole with an aspect ratio of 1:1. Which is ratio of the hole diameter to depth (not to exceed 0.25 mm). Previously, microvia was any hole less than or equal to 0.15 mm in diameter
With the advent of smartphones and hand-held electronic devices, microvias have evolved from single-level to stacked microvias that cross over multiple HDI layers. Sequential build-up (SBU) technology is used to fabricate HDI boards. The HDI layers are usually built up from a traditionally manufactured double-sided core board or multilayer PCB. The HDI layers are built on both sides of the traditional PCB one by one with microvias. The SBU process consists of several steps: layer lamination, via formation, via metallization, and via filling. There are multiple choices of materials and/or technologies for each step.
Microvias can be filled with different materials and processes:(1) filled with epoxy resin (b-stage) during a sequential lamination process step; (2) filled with non-conductive or conductive material other than copper as a separate processing step; (3) plated closed with electroplated copper; (4) screen printed closed with a copper paste. Buried microvias are required to be filled, while blind microvias on the external layers usually do not have any fill requirements. A stacked microvia is usually filled with electroplated copper to make electrical interconnections between multiple HDI layers and provide structural support for the outer level(s) of the microvia or for a component mounted on the outermost copper pad.
The reliability of HDI structure is one of the major constraints for its successful widespread implementation in the PCB industry. Good thermo-mechanical reliability of microvias is an essential part of HDI reliability. Many researchers and professionals have studied the reliability of microvias in HDI PCBs. The reliability of microvias depends on many factors such as microvia geometry parameters, dielectric material properties, and processing parameters.
Microvia reliability research has focused on experimental assessment of the reliability of single-level unfilled microvias, as well as finite element analysis on stress/strain distributions in single-level microvias and microvia fatigue life estimation. Microvia failures identified from the research include interfacial separation (separation between the base of the microvia and the target pad), barrel cracks, corner/knee cracks, and target pad cracks (also referred to as microvia pull out). These failures result from the thermomechanical stresses caused by coefficient of thermal expansion (CTE) mismatch, in the PCB thickness direction, between the metallization in a microvia structure and the dielectric materials surrounding the metal. The following paragraph highlights some of the microvia reliability research.
Ogunjimi et al.looked at the effect of manufacturing and design process variables on the fatigue life of microvias, including trace(conductor) thickness, layer or layers of the dielectric around the trace and in the microvia, via geometry, via wall angle, ductility coefficient of the conductor material, and strain concentration factor. Finite element models were created with different geometries, and ANOVA method was used to determine the significance of the different process variables. The ANOVA results showed that the strain concentration factor was the most important variable, followed with the ductility factor, metallization thickness, and via wall angle. Prabhu et al. conducted a finite element analysis (FEA) on an HDI microvia structure to determine the effect of accelerated temperature cycling and thermal shock. Liu et al. and Ramakrishna et al. conducted liquid-to-liquid and air-to-air thermal shock testing, respectively, to studied the effect of dielectric material properties and microvia geometry parameters, such as microvia diameter, wall angle and plating thickness, on microvia reliability. Andrews et al. investigated single-level microvia reliability using IST (interconnect stress test), and considered the effect of reflow cycles of lead-free solder. Wang and Lai investigated the potential failure sites of microvias using finite element modeling. They found that filled microvias have a lower stress than unfilled microvias. Choi and Dasgupta introduced microvia non-destructive inspection method in their work.
Although most microvia reliability research focuses on single-level microvias, Birchtested multiple-level stacked and staggered microvias using IST test. Weibull analysis on the test data showed that single- and 2-level stacked microvias last longer than 3- and 4-level microvias (e. g. 2-level stacked microvias experienced about 20 times more cycles to failure than 4-level stacked microvias).
One challenge for high density interconnect board development, is to fabricate reliable microvias, especially for stacked microvias, without resulting in incomplete filling, dimples, or voids in the copper plating process.The authors of have been investigating the risk of microvias in terms of voids and other defects using both experimental testing and finite element analysis. They found that incomplete copper filling increases the stress levels in microvias and hence decreases microvia fatigue life. As for voids, different voiding conditions, such as different void sizes, shapes, and locations result in different effects on microvia reliability. Small voids of a spherical shape lightly increase the microvia fatigue life, but extreme voiding conditions greatly reduce the duration of microvias. This team is currently developing a qualification method that the electronics industry can use to assess the risks with using an HDI circuit board that employs microvias.
Semiconductor device fabrication is the process used to create the integrated circuits that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.
Wire bonding is the method of making interconnections (ATJ) between an integrated circuit (IC) or other semiconductor device and its packaging during semiconductor device fabrication. Although less common, wire bonding can be used to connect an IC to other electronics or to connect from one printed circuit board (PCB) to another. Wire bonding is generally considered the most cost-effective and flexible interconnect technology and is used to assemble the vast majority of semiconductor packages. Wire bonding can be used at frequencies above 100 GHz.
Flexible electronics, also known as flex circuits, is a technology for assembling electronic circuits by mounting electronic devices on flexible plastic substrates, such as polyimide, PEEK or transparent conductive polyester film. Additionally, flex circuits can be screen printed silver circuits on polyester. Flexible electronic assemblies may be manufactured using identical components used for rigid printed circuit boards, allowing the board to conform to a desired shape, or to flex during its use. An alternative approach to flexible electronics suggests various etching techniques to thin down the traditional silicon substrate to few tens of micrometers to gain reasonable flexibility, referred to as flexible silicon.
Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size in electronics such as integrated circuits (ICs) decreases, the practical significance of this effect increases.
The back end of line (BEOL) is the second portion of IC fabrication where the individual devices get interconnected with wiring on the wafer, the metalization layer. Common metals are copper and aluminum. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.
Flat no-leads packages such as quad-flat no-leads (QFN) and dual-flat no-leads (DFN) physically and electrically connect integrated circuits to printed circuit boards. Flat no-leads, also known as micro leadframe (MLF) and SON, is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. Flat no-lead is a near chip scale plastic encapsulated package made with a planar copper lead frame substrate. Perimeter lands on the package bottom provide electrical connections to the PCB. Flat no-lead packages include an exposed thermal pad to improve heat transfer out of the IC. Heat transfer can be further facilitated by metal vias in the thermal pad. The QFN package is similar to the quad-flat package (QFP), and a ball grid array (BGA).
IPC, the Association Connecting Electronics Industries, is a trade association whose aim is to standardize the assembly and production requirements of electronic equipment and assemblies. It was founded in 1957 as the Institute for Printed Circuits. Its name was later changed to the Institute for Interconnecting and Packaging Electronic Circuits to highlight the expansion from bare boards to packaging and electronic assemblies. In 1999, the organization formally changed its name to IPC with the accompanying tagline, Association Connecting Electronics Industries.
In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.
In microelectronics, a three-dimensional integrated circuit is an integrated circuit manufactured by stacking silicon wafers or dies and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. 3D IC is just one of a host of 3D integration schemes that exploit the z-direction to achieve electrical performance benefits.
Electroless nickel immersion gold (ENIG) is a type of surface plating used for printed circuit boards. It consists of an electroless nickel plating covered with a thin layer of immersion gold, which protects the nickel from oxidation.
The thermal copper pillar bump, also known as the "thermal bump", is a thermoelectric device made from thin-film thermoelectric material embedded in flip chip interconnects for use in electronics and optoelectronic packaging, including: flip chip packaging of CPU and GPU integrated circuits (chips), laser diodes, and semiconductor optical amplifiers (SOA). Unlike conventional solder bumps that provide an electrical path and a mechanical connection to the package, thermal bumps act as solid-state heat pumps and add thermal management functionality locally on the surface of a chip or to another electrical component. The diameter of a thermal bump is 238 μm and 60 μm high.
Electronic components have a wide range of failure modes. These can be classified in various ways, such as by time or cause. Failures can be caused by excess temperature, excess current or voltage, ionizing radiation, mechanical shock, stress or impact, and many other causes. In semiconductor devices, problems in the device package may cause failures due to contamination, mechanical stress of the device, or open or short circuits.
Pad cratering is a mechanically induced fracture in the resin between copper foil and outermost layer of fiberglass of a printed circuit board (PCB). It may be within the resin or at the resin to fiberglass interface.
Physics of failure is a technique under the practice of Design for Reliability that leverages the knowledge and understanding of the processes and mechanisms that induce failure to predict reliability and improve product performance.
Carbon nanotubes (CNTs) can be thought of as rolled up single atomic layer graphite sheet to form a seamless cylinder. Depending on the direction on which they are rolled, CNTs can be semiconducting or metallic. Metallic carbon nanotubes have been identified as a possible interconnect material for the future technology generations and to replace copper (Cu) interconnects. Electron transport can go over long nanotube lengths, 1μm, enabling CNTs to carry very high currents (i.e. up to 109 Acm−2) with essentially no heating due to nearly 1D electronic structure. Despite the current saturation in CNTs at high fields, the mitigation of such effects is possible due to encapsulated nanowires.
Solder fatigue is the mechanical degradation of solder due to deformation under cyclic loading. This can often occur at stress levels below the yield stress of solder as a result of repeated temperature fluctuations, mechanical vibrations, or mechanical loads. Techniques to evaluate solder fatigue behavior include finite element analysis and semi-analytical closed form equations.
Conductive anodic filament, also called CAF, is a metallic filament that forms from an electrochemical migration process and is known to cause printed circuit board (PCB) failures.
In integrated circuits (ICs), interconnects are structures that connect two or more circuit elements together electrically. The design and layout of interconnects on an IC is vital to its proper function, performance, power efficiency, reliability, and fabrication yield. The material interconnects are made from depends on many factors. Chemical and mechanical compatibility with the semiconductor substrate, and the dielectric in between the levels of interconnect is necessary, otherwise barrier layers are needed. Suitability for fabrication is also required; some chemistries and processes prevent integration of materials and unit processes into a larger technology (recipe) for IC fabrication. In fabrication, interconnects are formed during the back-end-of-line after the fabrication of the transistors on the substrate.