SmartSpice

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SmartSpice is a commercial version of SPICE (Simulation Program with Integrated Circuit Emphasis) developed by Silvaco. SmartSpice is used to design complex analog circuits, analyze critical nets, characterize cell libraries, and verify analog mixed-signal designs. SmartSpice is compatible with popular analog design flows and foundry-supplied device models. It supports a reduced design space simulation environment. [1] Among its usages in the electronics industry is dynamic timing analysis. [2]

Contents

Key features

Supported transistor models

Supported input formats

Berkeley SPICE netlist, HSPICE netlist, W-element RLGC matrix files, S-parameter model files, Verilog-A and AMS, C/C++

Supported output formats

Rawfiles, output listings, Analysis results, Measurement data, Waveforms (portable across unix/windows platforms)

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References

  1. Chatterjee, Pallab. "Rounding Up Design Corners". Chip Design Mag. Retrieved 2010-04-14.
  2. Thimmannagari, Chandra (2005). CPU Design: Answers to Frequently Asked Questions . Springer. pp.  201. ISBN   038723800X.
  3. Marshall, Andrew; Natarajan, Sreedhar (2002). SOI Design. Springer. p. 71.