Type of RAM | |
Developer | JEDEC |
---|---|
Type | Synchronous dynamic random-access memory (SDRAM) |
Generation | 4th generation |
Release date | 2014 |
Standards |
|
Clock rate | 800–1600 MHz |
Voltage | Reference 1.2 V |
Predecessor | DDR3 SDRAM (2007) |
Successor | DDR5 SDRAM (2020) |
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface.
Released to the market in 2014, [2] [3] [4] it is a variant of dynamic random-access memory (DRAM), of which some have been in use since the early 1970s, [5] and a higher-speed successor to the DDR2 and DDR3 technologies.
DDR4 is not compatible with any earlier type of random-access memory (RAM) due to different signaling voltage and physical interface, besides other factors.
DDR4 SDRAM was released to the public market in Q2 2014, focusing on ECC memory, [6] while the non-ECC DDR4 modules became available in Q3 2014, accompanying the launch of Haswell-E processors that require DDR4 memory. [7]
The primary advantages of DDR4 over its predecessor, DDR3, include higher module density and lower voltage requirements, coupled with higher data rate transfer speeds. The DDR4 standard allows for DIMMs of up to 64 GB in capacity, compared to DDR3's maximum of 16 GB per DIMM. [1] [8] [ failed verification ]
Unlike previous generations of DDR memory, prefetch has not been increased above the 8n used in DDR3; [9] : 16 the basic burst size is eight 64-bit words, and higher bandwidths are achieved by sending more read/write commands per second. To allow this, the standard divides the DRAM banks into two or four selectable bank groups, [10] where transfers to different bank groups may be done more rapidly.
Because power consumption increases with speed, the reduced voltage allows higher speed operation without unreasonable power and cooling requirements.
DDR4 operates at a voltage of 1.2 V with a frequency between 800 and 1600 MHz (DDR4-1600 through DDR4-3200), compared to frequencies between 400 and 1067 MHz (DDR3-800 through DDR3-2133) [11] [lower-alpha 1] and voltage requirements of 1.5 V of DDR3. Due to the nature of DDR, speeds are typically advertised as doubles of these numbers (DDR3-1600 and DDR4-2400 are common, while DDR4-3200, DDR4-4800 and DDR4-5000 are available but at a higher cost). Unlike DDR3's 1.35 V low voltage standard DDR3L, there is no DDR4L low voltage version of DDR4. [13] [14]
In April 2013, a news writer at International Data Group (IDG) –an American technology research business originally part of IDC –produced an analysis of their perceptions related to DDR4 SDRAM. [43] The conclusions were that the increasing popularity of mobile computing and other devices using slower but low-powered memory, the slowing of growth in the traditional desktop computing sector, and the consolidation of the memory manufacturing marketplace, meant that margins on RAM were tight.
As a result, the desired premium pricing for the new technology was harder to achieve, and capacity had shifted to other sectors. SDRAM manufacturers and chipset creators were, to an extent, "stuck between a rock and a hard place" where "nobody wants to pay a premium for DDR4 products, and manufacturers don't want to make the memory if they are not going to get a premium", according to Mike Howard from iSuppli. [43] A switch in consumer sentiment toward desktop computing and release of processors having DDR4 support by Intel and AMD could therefore potentially lead to "aggressive" growth. [43]
Intel's 2014 Haswell roadmap, revealed the company's first use of DDR4 SDRAM in Haswell-EP processors. [44]
AMD's Ryzen processors, revealed in 2016 and shipped in 2017, use DDR4 SDRAM. [45]
This section needs to be updated.(January 2014) |
DDR4 chips use a 1.2 V supply [9] : 16 [46] [47] with a 2.5 V auxiliary supply for wordline boost called VPP, [9] : 16 as compared with the standard 1.5 V of DDR3 chips, with lower voltage variants at 1.35 V appearing in 2013. DDR4 is expected to be introduced at transfer rates of 2133 MT/s, [9] : 18 estimated to rise to a potential 4266 MT/s [39] by 2013. The minimum transfer rate of 2133 MT/s was said to be due to progress made in DDR3 speeds which, being likely to reach 2133 MT/s, left little commercial benefit to specifying DDR4 below this speed. [33] [39] Techgage interpreted Samsung's January 2011 engineering sample as having CAS latency of 13 clock cycles, described as being comparable to the move from DDR2 to DDR3. [31]
Internal banks are increased to 16 (4 bank select bits), with up to 8 ranks per DIMM. [9] : 16
Protocol changes include: [9] : 20
Increased memory density is anticipated, possibly using TSV ("through-silicon via") or other 3D stacking processes. [33] [39] [48] [49] The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC, [49] with provision for up to 8 stacked dies. [9] : 12 X-bit Labs predicted that "as a result DDR4 memory chips with very high density will become relatively inexpensive". [39]
Switched memory banks are also an anticipated option for servers. [33] [48]
In 2008 concerns were raised in the book Wafer Level 3-D ICs Process Technology that non-scaling analog elements such as charge pumps and voltage regulators, and additional circuitry "have allowed significant increases in bandwidth but they consume much more die area". Examples include CRC error-detection, on-die termination, burst hardware, programmable pipelines, low impedance, and increasing need for sense amps (attributed to a decline in bits per bitline due to low voltage). The authors noted that, as a result, the amount of die used for the memory array itself has declined over time from 70–78% for SDRAM and DDR1, to 47% for DDR2, to 38% for DDR3 and to potentially less than 30% for DDR4. [50]
The specification defined standards for ×4, ×8 and ×16 memory devices with capacities of 2, 4, 8 and 16 Gbit. [1] [51]
In addition to bandwidth and capacity variants, DDR4 modules can optionally implement:
Command | CS | BG1–0, BA1–0 | ACT | A17 | A16 RAS | A15 CAS | A14 WE | A13 | A12 BC | A11 | A10 AP | A9–0 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Deselect (no operation) | H | X | |||||||||||
Active (activate): open a row | L | Bank | L | Row address | |||||||||
No operation | L | V | H | V | H | H | H | V | |||||
ZQ calibration | L | V | H | V | H | H | L | V | Long | V | |||
Read (BC, burst chop) | L | Bank | H | V | H | L | H | V | BC | V | AP | Column | |
Write (AP, auto-precharge) | L | Bank | H | V | H | L | L | V | BC | V | AP | Column | |
Unassigned, reserved | L | V | v | V | L | H | H | V | |||||
Precharge all banks | L | V | H | V | L | H | L | V | H | V | |||
Precharge one bank | L | Bank | H | V | L | H | L | V | L | V | |||
Refresh | L | V | H | V | L | L | H | V | |||||
Mode register set (MR0–MR6) | L | Register | H | L | L | L | L | L | Data | ||||
|
Although it still operates in fundamentally the same way, DDR4 makes one major change to the command formats used by previous SDRAM generations. A new command signal, ACT, is low to indicate the activate (open row) command.
The activate command requires more address bits than any other (18 row address bits in a 16 Gbit part), so the standard RAS, CAS, and WE active low signals are shared with high-order address bits that are not used when ACT is high. The combination of RAS=L and CAS=WE=H that previously encoded an activate command is unused.
As in previous SDRAM encodings, A10 is used to select command variants: auto-precharge on read and write commands, and one bank vs. all banks for the precharge command. It also selects two variants of the ZQ calibration command.
As in DDR3, A12 is used to request burst chop: truncation of an 8-transfer burst after four transfers. Although the bank is still busy and unavailable for other commands until eight transfer times have elapsed, a different bank can be accessed.
Also, the number of bank addresses has been increased greatly. There are four bank select bits to select up to 16 banks within each DRAM: two bank address bits (BA0, BA1), and two bank group bits (BG0, BG1). There are additional timing restrictions when accessing banks within the same bank group; it is faster to access a bank in a different bank group.
In addition, there are three chip select signals (C0, C1, C2), allowing up to eight stacked chips to be placed inside a single DRAM package. These effectively act as three more bank select bits, bringing the total to seven (128 possible banks).
Standard transfer rates are 1600, 1866, 2133, 2400, 2666, 2933, and 3200 MT/s [53] [54] (12⁄15, 14⁄15, 16⁄15, 18⁄15, 20⁄15, 22⁄15, and 24⁄15 GHz clock frequencies, double data rate), with speeds up to DDR4-4800 (2400 MHz clock) commercially available. [55]
The DDR4 team at Micron Technology identified some key points for IC and PCB design: [56]
IC design: [56]
Circuit board design: [56]
Rowhammer mitigation techniques include larger storage capacitors, modifying the address lines to use address space layout randomization and dual-voltage I/O lines that further isolate potential boundary conditions that might result in instability at high write/read speeds.
DDR4 memory is supplied in 288-pin dual in-line memory modules (DIMMs), similar in size to 240-pin DDR3 DIMMs. The pins are spaced more closely (0.85 mm instead of 1.0) to fit the increased number within the same 5¼ inch (133.35 mm) standard DIMM length, but the height is increased slightly (31.25 mm/1.23 in instead of 30.35 mm/1.2 in) to make signal routing easier, and the thickness is also increased (to 1.2 mm from 1.0) to accommodate more signal layers. [57] DDR4 DIMM modules have a slightly curved edge connector so not all of the pins are engaged at the same time during module insertion, lowering the insertion force. [15]
DDR4 SO-DIMMs have 260 pins instead of the 204 pins of DDR3 SO-DIMMs, spaced at 0.5 rather than 0.6 mm, and are 2.0 mm wider (69.6 versus 67.6 mm), but remain the same 30 mm in height. [58]
For its Skylake microarchitecture, Intel designed a SO-DIMM package named UniDIMM, which can be populated with either DDR3 or DDR4 chips. At the same time, the integrated memory controller (IMC) of Skylake CPUs is announced to be capable of working with either type of memory. The purpose of UniDIMMs is to help in the market transition from DDR3 to DDR4, where pricing and availability may make it undesirable to switch the RAM type. UniDIMMs have the same dimensions and number of pins as regular DDR4 SO-DIMMs, but the edge connector's notch is placed differently to avoid accidental use in incompatible DDR4 SO-DIMM sockets. [59]
Standard name | Memory clock (MHz) | I/O bus clock (MHz) | Data rate (MT/s) [lower-alpha 3] | Module name | Peak trans- fer rate (GB/s) [lower-alpha 4] | Timings CL-tRCD-tRP | CAS latency (ns) |
---|---|---|---|---|---|---|---|
DDR4-1600J* DDR4-1600K DDR4-1600L | 200 | 800 | 1600 | PC4-12800 | 12.8 | 10-10-10 11-11-11 12-12-12 | 12.5 13.75 15 |
DDR4-1866L* DDR4-1866M DDR4-1866N | 233.33 | 933.33 | 1866.67 | PC4-14.900 | 14.9333 | 12-12-12 13-13-13 14-14-14 | 12.857 13.929 15 |
DDR4-2133N* DDR4-2133P DDR4-2133R | 266.67 | 1066.67 | 2133.33 | PC4-17000 | 17.06667 | 14-14-14 15-15-15 16-16-16 | 13.125 14.063 15 |
DDR4-2400P* DDR4-2400R DDR4-2400T DDR4-2400U | 300 | 1200 | 2400 | PC4-19200 | 19.2 | 15-15-15 16-16-16 17-17-17 18-18-18 | 12.5 13.32 14.16 15 |
DDR4-2666T DDR4-2666U DDR4-2666V DDR4-2666W | 333.33 | 1333.33 | 2666.67 | PC4-21300 | 21.3333 | 17-17-17 18-18-18 19-19-19 20-20-20 | 12.75 13.50 14.25 15 |
DDR4-2933V DDR4-2933W DDR4-2933Y DDR4-2933AA | 366.67 | 1466.67 | 2933.33 | PC4-23466 | 23.46667 | 19-19-19 20-20-20 21-21-21 22-22-22 | 12.96 13.64 14.32 15 |
DDR4-3200W DDR4-3200AA DDR4-3200AC | 400 | 1600 | 3200 | PC4-25600 | 25.6 | 20-20-20 22-22-22 24-24-24 | 12.5 13.75 15 |
DDR4-xxxx denotes per-bit data transfer rate, and is normally used to describe DDR chips. PC4-xxxxx denotes overall transfer rate, in megabytes per second, and applies only to modules (assembled DIMMs). Because DDR4 memory modules transfer data on a bus that is 8 bytes (64 data bits) wide, module peak transfer rate is calculated by taking transfers per second and multiplying by eight. [60]
At the 2016 Intel Developer Forum, the future of DDR5 SDRAM was discussed. The specifications were finalized at the end of 2016 – but no modules will be available before 2020. [61] Other memory technologies – namely HBM in version 3 and 4 [62] – aiming to replace DDR4 have also been proposed.
In 2011, JEDEC published the Wide I/O 2 standard; it stacks multiple memory dies, but does that directly on top of the CPU and in the same package. This memory layout provides higher bandwidth and better power performance than DDR4 SDRAM, and allows a wide interface with short signal lengths. It primarily aims to replace various mobile DDRX SDRAM standards used in high-performance embedded and mobile devices, such as smartphones. [63] [64] Hynix proposed similar High Bandwidth Memory (HBM), which was published as JEDEC JESD235. Both Wide I/O 2 and HBM use a very wide parallel memory interface, up to 512 bits wide for Wide I/O 2 (compared to 64 bits for DDR4), running at a lower frequency than DDR4. [65] Wide I/O 2 is targeted at high-performance compact devices such as smartphones, where it will be integrated into the processor or system on a chip (SoC) packages. HBM is targeted at graphics memory and general computing, while HMC targets high-end servers and enterprise applications. [65]
Micron Technology's Hybrid Memory Cube (HMC) stacked memory uses a serial interface. Many other computer buses have migrated towards replacing parallel buses with serial buses, for example by the evolution of Serial ATA replacing Parallel ATA, PCI Express replacing PCI, and serial ports replacing parallel ports. In general, serial buses are easier to scale up and have fewer wires/traces, making circuit boards using them easier to design. [66] [67] [68]
In the longer term, experts speculate that non-volatile RAM types like PCM (phase-change memory), RRAM (resistive random-access memory), or MRAM (magnetoresistive random-access memory) could replace DDR4 SDRAM and its successors. [69]
GDDR5 SGRAM is a graphics type of DDR3 synchronous graphics RAM, which was introduced before DDR4, and is not a successor to DDR4.
Double Data Rate Synchronous Dynamic Random-Access Memory is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM and DDR5 SDRAM. None of its successors are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, DDR4 and DDR5 memory modules will not work on DDR1-equipped motherboards, and vice versa.
Synchronous dynamic random-access memory is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.
A DIMM, or Dual In-Line Memory Module, is a popular type of memory module used in computers. It is a printed circuit board with one or both sides holding DRAM chips and pins. The vast majority of DIMMs are standardized through JEDEC standards, although there are proprietary DIMMs. DIMMs come in a variety of speeds and sizes, but generally are one of two lengths - PC which are 133.35 mm (5.25 in) and laptop (SO-DIMM) which are about half the size at 67.60 mm (2.66 in).
Double Data Rate 2 Synchronous Dynamic Random-Access Memory is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It is a JEDEC standard (JESD79-2); first published in September 2003. DDR2 succeeded the original DDR SDRAM specification, and was itself succeeded by DDR3 SDRAM in 2007. DDR2 DIMMs are neither forward compatible with DDR3 nor backward compatible with DDR.
In computing, double data rate (DDR) describes a computer bus that transfers data on both the rising and falling edges of the clock signal and hence doubles the memory bandwidth by transferring data twice per clock cycle. This is also known as double pumped, dual-pumped, and double transition. The term toggle mode is used in the context of NAND flash memory.
In the fields of digital electronics and computer hardware, multi-channel memory architecture is a technology that increases the data transfer rate between the DRAM memory and the memory controller by adding more channels of communication between them. Theoretically, this multiplies the data rate by exactly the number of channels present. Dual-channel memory employs two channels. The technique goes back as far as the 1960s having been used in IBM System/360 Model 91 and in CDC 6600.
In computing, serial presence detect (SPD) is a standardized way to automatically access information about a memory module. Earlier 72-pin SIMMs included five pins that provided five bits of parallel presence detect (PPD) data, but the 168-pin DIMM standard changed to a serial presence detect to encode more information.
Double Data Rate 3 Synchronous Dynamic Random-Access Memory is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors.
The "32 nm" node is the step following the "45 nm" process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch of a memory cell at this technology level.
A Fully Buffered DIMM (FB-DIMM) is a type of memory module used in computer systems. It is designed to improve memory performance and capacity by allowing multiple memory modules to be each connected to the memory controller using a serial interface, rather than a parallel one. Unlike the parallel bus architecture of traditional DRAMs, an FB-DIMM has a serial interface between the memory controller and the advanced memory buffer (AMB). Conventionally, data lines from the memory controller have to be connected to data lines in every DRAM module, i.e. via multidrop buses. As the memory width increases together with the access speed, the signal degrades at the interface between the bus and the device. This limits the speed and memory density, so FB-DIMMs take a different approach to solve the problem.
GDDR4 SDRAM, an abbreviation for Graphics Double Data Rate 4 Synchronous Dynamic Random-Access Memory, is a type of graphics card memory (SGRAM) specified by the JEDEC Semiconductor Memory Standard. It is a rival medium to Rambus's XDR DRAM. GDDR4 is based on DDR3 SDRAM technology and was intended to replace the DDR2-based GDDR3, but it ended up being replaced by GDDR5 within a year.
In computing, a memory module or RAM stick is a printed circuit board on which memory integrated circuits are mounted.
Memory timings or RAM timings describe the timing information of a memory module or the onboard LPDDRx. Due to the inherent qualities of VLSI and microelectronics, memory chips require time to fully execute commands. Executing commands too quickly will result in data corruption and results in system instability. With appropriate time between commands, memory modules/chips can be given the opportunity to fully switch transistors, charge capacitors and correctly signal back information to the memory controller. Because system performance depends on how fast memory can be used, this timing directly affects the performance of the system.
Low-Power Double Data Rate (LPDDR), also known as LPDDR SDRAM, is a type of synchronous dynamic random-access memory that consumes less power and is targeted for mobile computers and devices such as mobile phones. Older variants are also known as Mobile DDR, and abbreviated as mDDR.
HyperCloud Memory (HCDIMM) is a DDR3 SDRAM dual in-line memory module (DIMM) used in server applications requiring a great deal of memory. It was initially launched in 2009 at the International Supercomputing Conference by Irvine, California, based company, Netlist Inc. It was never a JEDEC standard, and the main server vendors supporting it were IBM and Hewlett Packard Enterprise.
A NVDIMM or non-volatile DIMM is a type of persistent random-access memory for computers using widely used DIMM form-factors. Non-volatile memory is memory that retains its contents even when electrical power is removed, for example from an unexpected power loss, system crash, or normal shutdown. Properly used, NVDIMMs can improve application performance and system crash recovery time. They enhance solid-state drive (SSD) endurance and reliability.
Double Data Rate 5 Synchronous Dynamic Random-Access Memory is the latest type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 was planned to reduce power consumption, while doubling bandwidth. The standard, originally targeted for 2018, was released on July 14, 2020.
UniDIMM is a specification for dual in-line memory modules (DIMMs), which are printed circuit boards (PCBs) designed to carry dynamic random-access memory (DRAM) chips. UniDIMMs can be populated with either DDR3 or DDR4 chips, with no support for any additional memory control logic; as a result, the computer's memory controller must support both DDR3 and DDR4 memory standards. The UniDIMM specification was created by Intel for its Skylake microarchitecture, whose integrated memory controller (IMC) supports both DDR3 and DDR4 memory technologies.
High Bandwidth Memory (HBM) is a computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerators, network devices, high-performance datacenter AI ASICs, as on-package cache in CPUs and on-package RAM in upcoming CPUs, and FPGAs and in some supercomputers. The first HBM memory chip was produced by SK Hynix in 2013, and the first devices to use HBM were the AMD Fiji GPUs in 2015.
Row hammer is a computer security exploit that takes advantage of an unintended and undesirable side effect in dynamic random-access memory (DRAM) in which memory cells interact electrically between themselves by leaking their charges, possibly changing the contents of nearby memory rows that were not addressed in the original memory access. This circumvention of the isolation between DRAM memory cells results from the high cell density in modern DRAM, and can be triggered by specially crafted memory access patterns that rapidly activate the same memory rows numerous times.
Initial investigations have already started on memory technology beyond DDR3. JEDEC always has about three generations of memory in various stages of the standardization process: current generation, next generation, and future.
DDR3 memory launched in June 2007
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: CS1 maint: unfit URL (link)The JEDEC standardisation committee cited similar figures around one year ago
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