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HDL simulators are software packages that simulate expressions written in one of the hardware description languages, such as VHDL, Verilog, SystemVerilog.
This page is intended to list current and historical HDL simulators, accelerators, emulators, etc.
| Simulator name | Author/company | Languages | Description |
|---|---|---|---|
| Active-HDL / Riviera-PRO | Aldec | VHDL-1987,-1993,-2002,-2008,-2019 V1995, V2001, V2005, SV2009, SV2012, SV2017 | Active-HDL is Aldec's Windows-based simulator with complete HDL graphical entry and verification environment aimed at FPGA and SoC FPGA applications. Riviera-PRO is Aldec's Windows/Linux-based simulator with complete verification environment aimed at FPGA, SoC FPGA and ASIC applications. Both Aldec simulators are the most cost-effective simulators in the industry, with advanced debugging capabilities and high-performance simulation engines, supports advanced verification methodologies such as assertion based verification and UVM. Aldec simulators have the complete VHDL-2008 implementation and the first to offer VHDL-2019 features. Aldec has the most cost-effective commercial simulator in the industry. |
| Aeolus-DS | Huada Empyrean Software Co., Ltd | V2001 | Aeolus-DS is a part of Aeolus simulator which is designed to simulate mixed signal circuit. Aeolus-DS supports pure Verilog simulation. |
| HiLo | Teradyne | Used in 1980s. | |
| Incisive Enterprise Simulator ('big 3') | Cadence Design Systems | VHDL-1987,-1993,-2002,-2008, V2001, SV2005, SV2009, SV2012, SV2017 | Cadence initially acquired Gateway Design, thereby acquiring Verilog-XL. In response to competition from faster simulators, Cadence developed its own compiled-language simulator, NC-Verilog. The modern version of the NCsim family, called Incisive Enterprise Simulator, includes Verilog, VHDL, and SystemVerilog support. It also provides support for the e verification language, and a fast SystemC simulation kernel. |
| ISE Simulator | Xilinx | VHDL-93, V2001 | Xilinx's simulator comes bundled with the ISE Design Suite. ISE Simulator (ISim) provides support for mixed-mode language simulation including, but not limited to, simulation of designs targeted for Xilinx's FPGAs and CPLDs. |
| Metrics Cloud Simulator | Metrics Technologies | SV2012 | SystemVerilog simulator used on the Metrics cloud platform. Includes all the standard features of a modern SystemVerilog simulator including debug, APIs, language and testbench support. |
| ModelSim / Questa ('big 3') | Mentor Graphics | VHDL-1987,-1993,-2002,-2008, V2001, SV2005, SV2009, SV2012, SV2017 | The original Modeltech (VHDL) simulator was the first mixed-language simulator capable of simulating VHDL and Verilog design entities together. In 2003, ModelSim 5.8 was the first simulator to begin supporting features of the Accellera SystemVerilog 3.0 standard. [1] In 2005 Mentor introduced Questa to provide high performance Verilog and SystemVerilog simulation and expand Verification capabilities to more advanced methodologies such as Assertion Based Verification and Functional Coverage. Today Questa is the leading high performance SystemVerilog and Mixed simulator supporting a full suite of methodologies including industry standard OVM and UVM. ModelSim is still the leading simulator for FPGA design. |
| MPSim | Axiom Design Automation | V2001, V2005, SV2005, SV2009 | MPsim is a fast compiled simulator with full support for Verilog, SystemVerilog and SystemC. It includes Designer, integrated Verilog and SystemVerilog debugging environment and has built-in support for multi-cpu simulation. |
| PureSpeed | Frontline | V1995 | The first Verilog simulator available on the Windows OS. The simulator had a cycle-based counterpart called 'CycleDrive'. FrontLine was sold to Avant! in 1998, which was later acquired by Synopsys in 2002. Synopsys discontinued Purespeed in favor of its well-established VCS simulator. |
| Quartus II Simulator (Qsim) | Altera | VHDL-1993, V2001, SV2005 | Altera's simulator bundled with the Quartus II design software in release 11.1 and later. Supports Verilog, VHDL and AHDL. |
| SILOS | Silvaco | V2001 | As one of the low-cost interpreted Verilog simulators, Silos III, from SimuCad, enjoyed great popularity in the 1990s. With Silvaco's acquisition of SimuCad, Silos is part of the Silvaco EDA tool suite. |
| SIMILI VHDL | Symphony EDA | VHDL-1993 | Another low-cost VHDL simulator with graphical user interface and integrated waveform viewer. Their web site was not updated for quite some time now. You can no longer purchase the software. The free version does work but you have to request a license via email. |
| SMASH | Dolphin Integration | V1995, V2001, VHDL-1993 | SMASH is a mixed-signal, multi-language simulator for IC or PCB designs. It uses SPICE syntax for analog descriptions, Verilog-HDL and VHDL for digital, Verilog-A/AMS, VHDL-AMS and ABCD (a combination of SPICE and C) for analog behavioral, and C for DSP algorithms. |
| Speedsim | Cadence Design Systems | V1995 | Cycle based simulator originally developed at DEC. The DEC developers spun off to form Quickturn Design Systems. Quickturn was later acquired by Cadence, who discontinued the product in 2005. Speedsim featured an innovative slotted bit-slice architecture that supported simulation of up to 32 tests in parallel. |
| Super-FinSim | Fintronic | V2001 | This simulator is available on multi-platform, claiming IEEE 1364-2001 compliance. |
| TEGAS / Texsim | TEGAS/CALMA/GE | TDL (Tegas Design Language) | First described in 1972 paper, used in 1980s by ASIC vendors such as LSI Logic, GE. |
| VCS ('big 3') | Synopsys | VHDL-1987,-1993,-2002,-2008, V2001, SV2005, SV2009, SV2012, SV2017 | Originally developed by John Sanguinetti, Peter Eichenberger and Michael McNamara under the startup company Chronologic Simulation, which was acquired by ViewLogic Systems in 1994. ViewLogic was subsequently acquired by Synopsys in 1997. VCS has been in continuous active development, and pioneered compiled-code simulation, native testbench and SystemVerilog support, and unified compiler technologies. Today, VCS provides comprehensive support for all functional verification methodologies and languages (including VHDL, Verilog, SystemVerilog, Verilog AMS, SystemC, and C/C++), and advanced simulation technologies including native low power, x-propagation, unreachability analysis, and fine-grained parallelism. |
| Verilogger Extreme / Pro | SynaptiCAD | V2001, V1995 | Verilogger Pro is a low-cost interpreted simulator based on Elliot Mednick's VeriWell code base. Verilogger Extreme is a newer, compiled-code simulator that is Verilog-2001 compliant and much faster than Pro. |
| Verilog-XL | Cadence Design Systems | V1995 | The original Verilog simulator, Gateway Design's Verilog-XL was the first (and only, for a time) Verilog simulator to be qualified for ASIC (validation) sign-off. After its acquisition by Cadence Design Systems, Verilog-XL changed very little over the years, retaining an interpreted language engine, and freezing language-support at Verilog-1995. Cadence recommends Incisive Enterprise Simulator for new design projects, as XL no longer receives active development. Nevertheless, XL continues to find use in companies with large codebases of legacy Verilog. Many early Verilog codebases will only simulate properly in Verilog-XL, due to variation in language implementation of other simulators. |
| Veritak | Sugawara Systems | V2001 | It is low-cost and Windows-based only. It boasts a built-in waveform viewer and fast execution. |
| Xilinx Simulator (XSIM) | Xilinx | VHDL-1993,-2002 (subset),-2008 (subset), [2] V2001, V2005, SV2009, SV2012, SV2017 | Xilinx Simulator (XSIM) comes as part of the Vivado design suite. It is a compiled-language simulator that supports mixed language simulation with Verilog, SystemVerilog, VHDL and SystemC language. It supports standard debugging tool such as step through code, breakpoints, cross-probing, value probes, call stack and local variable Window. The waveform viewer in Xilinx Simulator supports virtual bus, signal grouping, analog view & protocol viewing features. It also supports UVM 1.2 and functional coverage for advanced verification. It supports both GUI and batch mode via TCL script and allows simulation of encrypted IPs. Xilinx Simulator supports SystemVerilog Direct Programming Interface (DPI) and Xilinx simulator interface (XSI) to connect C/C++ model with Xilinx simulator. |
| Z01X | WinterLogic (acquired by Synopsys 2016) | V2001, SV2005 | Developed as a fault simulator but can also be used as a logic simulator. |
Some commercial proprietary simulators (such as ModelSim) are available in student, or evaluation/demo editions. These editions generally have many features disabled, arbitrary limits on simulation design size, but are sometimes offered free of charge.
| Simulator name | License | Author/company | Supported languages | Description |
|---|---|---|---|---|
| Cascade | BSD | VMware Research | V2005 (large subset) | Just-in-Time Verilog simulator and compiler for FPGAs allowing to instantly run both synthesizable and unsynthesizable Verilog on hardware |
| CVC | Perl style artistic license [3] | Tachyon Design Automation | V2001, V2005 | CVC is a Verilog HDL compiled simulator. CVC has the ability to simulate in either interpreted or compiled mode. |
| GPL Cver | GPL | Pragmatic C Software | V1995, minimal V2001 | This is a GPL open-source simulator. It is a pure simulator. This simulator is not fully IEEE 1364-2001 compliant. It does not support generate and constant functions. |
| Icarus Verilog | GPL2+ | Stephen Williams | V1995, V2001, V2005, limited SV2005/SV2009/SV2012 | Also known as iverilog. Good support for Verilog 2005, including generate statements and constant functions. |
| Isotel Mixed Signal & Domain Simulation | GPL | ngspice, Yosys communities and Isotel | V2005 | Open-source mixed signal ngspice simulator in combination with verilog synthesis software called Yosys and Isotel extension for embedded C/C++ (or other) co-simulation. |
| LIFTING | A. Bosio, G. Di Natale (LIRMM) | V1995 | LIFTING (LIRMM Fault Simulator) is an open-source simulator able to perform both logic and fault simulation for single/multiple stuck-at faults and single event upset (SEU) on digital circuits described in Verilog. | |
| OSS CVC | Perl style artistic license | Tachyon Design Automation | V2001, V2005 | CVC is a Verilog HDL compiled simulator. CVC has the ability to simulate in either interpreted or compiled mode. Source code is available under a Perl style artistic license. |
| TkGate | GPL2+ | Jeffery P. Hansen | V1995 | Event driven digital circuit editor and simulator with tcl/tk GUI based on Verilog. Includes Verilog simulator Verga. |
| Verilator | GPL3 | Veripool | V1995, V2001, V2005, SV2005, SV2009, SV2012, SV2017, SV2023 | Verilator is a very high speed open-source simulator that compiles Verilog to multithreaded C++/SystemC. Verilator previously required that testbench code be written as synthesizable RTL, or as a C++ or SystemC testbench, because Verilator did not support behavioral Verilog. These are now supported. |
| Verilog Behavioral Simulator (VBS) | GPL | Lay H. Tho and Jimen Ching | V1995 | Supports functions, tasks and module instantiation. It has a few features, but this release has enough for a VLSI student to use and learn Verilog. Supports only behavioral constructs of Verilog and minimal simulation constructs such as 'initial' statements. |
| VeriWell | GPL2 | Elliot Mednick | V1995 | This simulator used to be proprietary, but has recently become GPL open-source. Compliance with 1364 is not well documented. It is not fully compliant with IEEE 1364–1995. |
| Simulator name | License | Author/company | Supported languages | Description |
|---|---|---|---|---|
| FreeHDL | GPL2+ | Edwin Naroska | VHDL-1987, VHDL-1993 | A project to develop a free, open source, VHDL simulator |
| GHDL | GPL2+ | Tristan Gingold | VHDL-1987, VHDL-1993, VHDL-2002, partial VHDL-2008, partial VHDL-2019 [4] | GHDL is a complete VHDL simulator, using the GCC technology. |
| NVC | GPL-3.0-or-later | Nick Gasson and contributors | VHDL-1993, VHDL-2002, VHDL-2008, partial VHDL-2019 [5] | NVC is a GPLv3 VHDL compiler and simulator. It is available for various distributions of Linux, macOS, Windows (via Cygwin or MSYS2), and OpenBSD. |
| Tag | Description |
|---|---|
| V1995 | IEEE 1364-1995 Verilog |
| V2001 | IEEE 1364-2001 Verilog |
| V2005 | IEEE 1364-2005 Verilog |
| SV2005 | IEEE 1800-2005 SystemVerilog |
| SV2009 | IEEE 1800-2009 SystemVerilog |
| SV2012 | IEEE 1800-2012 SystemVerilog |
| SV2017 | IEEE 1800-2017 SystemVerilog |
| SV2023 | IEEE 1800-2023 SystemVerilog |
| VHDL-1987 | IEEE 1076-1987 VHDL |
| VHDL-1993 | IEEE 1076-1993 VHDL |
| VHDL-2002 | IEEE 1076-2002 VHDL |
| VHDL-2008 | IEEE 1076-2008 VHDL |
| VHDL-2019 | IEEE 1076-2019 VHDL |
The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes. Since 1987, VHDL has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE Std 1076; the latest version of which is IEEE Std 1076-2019. To model analog and mixed-signal systems, an IEEE-standardized HDL based on VHDL called VHDL-AMS has been developed.
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits. In 2009, the Verilog standard was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog has been officially part of the SystemVerilog language. The current version is IEEE standard 1800-2023.
In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, most commonly to design ASICs and program FPGAs.
SystemC is a set of C++ classes and macros which provide an event-driven simulation interface. These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax. SystemC processes can communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined. In certain respects, SystemC deliberately mimics the hardware description languages VHDL and Verilog, but is more aptly described as a system-level modeling language.
SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008, Verilog is now part of the same IEEE standard. It is commonly used in the semiconductor and electronic design industry as an evolution of Verilog.
Specman is an EDA tool that provides advanced automated functional verification of hardware designs. It provides an environment for working with, compiling, and debugging testbench environments written in the e Hardware Verification Language. Specman also offers automated testbench generation to boost productivity in the context of block, chip, and system verification.
Quite Universal Circuit Simulator (Qucs) is a free-software electronics circuit simulator software application released under GPL. It offers the ability to set up a circuit with a graphical user interface and simulate the large-signal, small-signal and noise behaviour of the circuit. Pure digital simulations are also supported using VHDL and/or Verilog. Only a small set of digital devices like flip flops and logic gates can be used with analog circuits. Qucs uses its own SPICE-incompatible backend simulator Qucsator, however the Qucs-S fork supports some SPICE backends.
Verilog-AMS is a derivative of the Verilog hardware description language that includes Analog and Mixed-Signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator, which solves the differential equations in analog-domain. Both domains are coupled: analog events can trigger digital actions and vice versa.
Intel Quartus Prime is programmable logic device design software produced by Intel; prior to Intel's acquisition of Altera the tool was called Altera Quartus Prime, earlier Altera Quartus II. Quartus Prime enables analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Quartus Prime includes an implementation of VHDL and Verilog for hardware description, visual editing of logic circuits, and vector waveform simulation.
C to HDL tools convert C language or C-like computer code into a hardware description language (HDL) such as VHDL or Verilog. The converted code can then be synthesized and translated into a hardware device such as a field-programmable gate array. Compared to software, equivalent designs in hardware consume less power and execute faster with lower latency, more parallelism and higher throughput. However, system design and functional verification in a hardware description language can be tedious and time-consuming, so systems engineers often write critical modules in HDL and other modules in a high-level language and synthesize these into HDL through C to HDL or high-level synthesis tools.
Flow to HDL tools and methods convert flow-based system design into a hardware description language (HDL) such as VHDL or Verilog. Typically this is a method of creating designs for field-programmable gate array, application-specific integrated circuit prototyping and digital signal processing (DSP) design. Flow-based system design is well-suited to field-programmable gate array design as it is easier to specify the innate parallelism of the architecture.
Electronic circuit simulation uses mathematical models to replicate the behavior of an actual electronic device or circuit. Simulation software allows for modeling of circuit operation and is an invaluable analysis tool. Due to its highly accurate modeling capability, many colleges and universities use this type of software for the teaching of electronics technician and electronics engineering programs. Electronics simulation software engages its users by integrating them into the learning experience. These kinds of interactions actively engage learners to analyze, synthesize, organize, and evaluate content and result in learners constructing their own knowledge.
Semulation is a computer science-related portmanteau of simulation and emulation, signifying the process of controlling an emulation through a simulator.
Aldec, Inc. is a privately owned electronic design automation company based in Henderson, Nevada that provides software and hardware used in creation and verification of digital designs targeting FPGA and ASIC technologies.
A waveform viewer is a software tool for viewing the signal levels of either a digital or analog circuit design.
Within computing, the Rosetta system-level specification language is a design language for complex, heterogeneous systems. Specific language design objectives include:
ModelSim is a multi-language environment by Siemens for simulation of hardware description languages such as VHDL, Verilog and SystemC, and includes a built-in C debugger. ModelSim can be used independently, or in conjunction with Intel Quartus Prime, PSIM, Xilinx ISE or Xilinx Vivado. Simulation is performed using the graphical user interface (GUI), or automatically using scripts.
MyHDL is a Python-based hardware description language (HDL).
Xilinx ISE is a discontinued software tool from Xilinx for synthesis and analysis of HDL designs, which primarily targets development of embedded firmware for Xilinx FPGA and CPLD integrated circuit (IC) product families. It was succeeded by Xilinx Vivado. Use of the last released edition from October 2013 continues for in-system programming of legacy hardware designs containing older FPGAs and CPLDs otherwise orphaned by the replacement design tool, Vivado Design Suite.