Interposer

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BGA with an interposer between the integrated circuit die to ball grid array BGA Package Sideview.svg
BGA with an interposer between the integrated circuit die to ball grid array
Pentium II: example of an interposer in dark yellow, integrated circuit die to ball grid array chip carrier Intel Pentium II die-to-BGA-interposter.png
Pentium II: example of an interposer in dark yellow, integrated circuit die to ball grid array chip carrier

An interposer is an electrical interface routing between one socket or connection to another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to a different connection. [1]

Interposer comes from the Latin word "interpōnere", meaning "to put between". [2] They are often used in BGA packages, multi-chip modules and high bandwidth memory. [3]

A common example of an interposer is an integrated circuit die to BGA, such as in the Pentium II. This is done through various substrates, both rigid and flexible, most commonly FR4 for rigid, and polyimide for flexible. [1] Silicon and glass are also evaluated as an integration method. [4] [5] Interposer stacks are also a widely accepted, cost-effective alternative to 3D ICs. [6] [7] There are already several products with interposer technology in the market, notably the AMD Fiji/Fury GPU, [8] and the Xilinx Virtex-7 FPGA. [9] In 2016, CEA Leti demonstrated their second generation 3D-NoC technology which combines small dies ("chiplets"), fabricated at the FDSOI 28 nm node, on a 65 nm CMOS interposer. [10]

Another example of an interposer is the adapter used to plug a SATA drive into a SAS backplane with redundant ports. While SAS drives have two ports that can be used to connect to redundant paths or storage controllers, SATA drives only have a single port. Directly, they can only connect to a single controller or path. SATA drives can be connected to nearly all SAS backplanes without adapters, but using an interposer with a port switching logic allows providing path redundancy. [11]

See also

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<span class="mw-page-title-main">SATA</span> Computer bus interface for storage devices

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JTAG is an industry standard for verifying designs of and testing printed circuit boards after manufacture.

<span class="mw-page-title-main">Land grid array</span> Type of surface-mount packaging for integrated circuits

The land grid array (LGA) is a type of surface-mount packaging for integrated circuits (ICs) that is notable for having the pins on the socket — as opposed to pins on the integrated circuit, known as a pin grid array (PGA). An LGA can be electrically connected to a printed circuit board (PCB) either by the use of a socket or by soldering directly to the board.

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<span class="mw-page-title-main">Serial Attached SCSI</span> Point-to-point serial protocol for enterprise storage

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<span class="mw-page-title-main">Multi-chip module</span> Electronic assembly containing multiple integrated circuits that behaves as a unit

A multi-chip module (MCM) is generically an electronic assembly where multiple integrated circuits, semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC. Other terms for MCM packaging include "heterogeneous integration" or "hybrid integrated circuit". The advantage of using MCM packaging is it allows a manufacturer to use multiple components for modularity and/or to improve yields over a conventional monolithic IC approach.

<span class="mw-page-title-main">System in a package</span> Electronic component

A system in a package (SiP) or system-in-package is a number of integrated circuits (ICs) enclosed in one chip carrier package or encompassing an IC package substrate that may include passive components and perform the functions of an entire system. The ICs may be stacked using package on package, placed side by side, and/or embedded in the substrate. The SiP performs all or most of the functions of an electronic system, and is typically used when designing components for mobile phones, digital music players, etc. Dies containing integrated circuits may be stacked vertically on the package substrate. They are internally connected by fine wires that are bonded to the package substrate. Alternatively, with a flip chip technology, solder bumps are used to join stacked chips together and to the package substrate, or even both techniques can be used in a single package. SiPs are like systems on a chip (SoCs) but less tightly integrated and not on a single semiconductor die.

<span class="mw-page-title-main">Memory module</span>

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A three-dimensional integrated circuit is a MOS integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics.

<span class="mw-page-title-main">Integrated passive devices</span>

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<span class="mw-page-title-main">Wafer-level packaging</span> Means of packaging an integrated circuit

Wafer-level packaging (WLP) is a process in integrated circuit manufacturing where packaging components are attached to an integrated circuit (IC) before the wafer – on which the IC is fabricated – is diced. In WLP, the top and bottom layers of the packaging and the solder bumps are attached to the integrated circuits while they are still in the wafer. This process differs from a conventional process, in which the wafer is sliced into individual circuits (dice) before the packaging components are attached.

Virtex is the flagship family of FPGA products currently developed by AMD, originally Xilinx before being acquired by the former. Other current product lines include Kintex (mid-range) and Artix (low-cost), each including configurations and models optimized for different applications. In addition, AMD offers the Spartan low-cost series, which continues to be updated and is nearing production utilizing the same underlying architecture and process node as the larger 7-series devices.

Hybrid Memory Cube (HMC) is a high-performance computer random-access memory (RAM) interface for through-silicon via (TSV)-based stacked DRAM memory. HMC competes with the incompatible rival interface High Bandwidth Memory (HBM).

<span class="mw-page-title-main">High Bandwidth Memory</span> Type of memory used on processors that require high transfer rate memory

High Bandwidth Memory (HBM) is a computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerators, network devices, high-performance datacenter AI ASICs, as on-package cache in CPUs and on-package RAM in upcoming CPUs, and FPGAs and in some supercomputers. The first HBM memory chip was produced by SK Hynix in 2013, and the first devices to use HBM were the AMD Fiji GPUs in 2015.

A 2.5D integrated circuit is an advanced packaging technique that combines multiple integrated circuit dies in a single package without stacking them into a three-dimensional integrated circuit (3D-IC) with through-silicon vias (TSVs). The term "2.5D" originated when 3D-ICs with TSVs were quite new and still very difficult. Chip designers realized that many of the advantages of 3D integration could be approximated by placing bare dies side by side on an interposer instead of stacking them vertically. If the pitch is very fine and the interconnect very short, the assembly can be packaged as a single component with better size, weight, and power characteristics than a comparable 2D circuit board assembly. This half-way 3D integration was facetiously named "2.5D" and the name stuck. Since then, 2.5D has proven to be far more than just "half-way to 3D." Some benefits:

Glossary of microelectronics manufacturing terms

Advanced packaging is the aggregation and interconnection of components before traditional integrated circuit packaging where a single die is packaged. Advanced packaging allows multiple devices, including electrical, mechanical, or semiconductor devices, to be merged and packaged as a single electronic device. Advanced packaging uses processes and techniques that are typically performed at semiconductor fabrication facilities, unlike traditional integrated circuit packaging, which does not. Advanced packaging thus sits between fabrication and traditional packaging -- or, in other terminology, between BEoL and post-fab. Advanced packaging includes multi-chip modules, 3D ICs, 2.5D ICs, heterogeneous integration, fan-out wafer-level packaging, system-in-package, quilt packaging, combining logic (processors) and memory in a single package, die stacking, several chiplets or dies in a package, combinations of these techniques, and others. 2.5D and 3D ICs are also called 2.5D or 3D packages.

References

  1. 1 2 Package Substrates/Interposers
  2. interposes - definition of interposes by the Free Online Dictionary, Thesaurus and Encyclopedia
  3. "2.5D".
  4. Silicon interposers: building blocks for 3D-ICs Archived 2018-01-30 at the Wayback Machine / ElectroIQ, 2011
  5. 2.5D Interposers; Organics vs. Silicon vs. Glass Archived 2015-10-10 at the Wayback Machine / Rao R. Tummala, ChipScaleReview Volume 13, Number 4, July–August 2013, pages 18-19
  6. Lau, John H. (2011-01-01). "The Most Cost-Effective Integrator (TSV Interposer) for 3D IC Integration System-in-Package (SiP)". ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1. pp. 53–63. doi:10.1115/ipack2011-52189. ISBN   978-0-7918-4461-8.
  7. "SEMICON Singapore 3D IC Wrap-Up: Bring down the cost and bring out the TSV alternatives - 3D InCites". 3D InCites. 2013-05-22. Retrieved 2017-08-21.
  8. "The AMD Radeon R9 Fury X Review: Aiming For the Top" . Retrieved 2017-08-17.
  9. "White Paper: Virtex-7 FPGAs" (PDF).
  10. "Leti Unveils New 3D Network-on-Chip | EE Times". EETimes. Archived from the original on 2016-07-15. Retrieved 2017-08-17.
  11. Willis Whittington (2007). "Desktop, Nearline & Enterprise Disk Drives" (PDF). Storage Networking Industry Association (SNIA). p. 17. Retrieved 2014-09-22.