Hardware watermarking

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Hardware watermarking, also known as IP core watermarking is the process of embedding covert marks as design attributes inside a hardware or IP core design itself. Hardware Watermarking can represent watermarking of either DSP Cores (widely used in consumer electronics devices) or combinational/sequential circuits. Both forms of Hardware Watermarking are very popular. In DSP Core Watermarking a secret mark is embedded within the logic elements of the DSP Core itself. DSP Core Watermark usually implants this secret mark in the form of a robust signature either in the RTL design or during High Level Synthesis (HLS) design. The watermarking process of a DSP Core leverages on the High Level Synthesis framework and implants a secret mark in one (or more) of the high level synthesis phases such as scheduling, allocation and binding. DSP Core Watermarking is performed to protect a DSP core from hardware threats such as IP piracy, forgery and false claim of ownership. [1] [2] [3] [4] Some examples of DSP cores are FIR filter, IIR filter, FFT, DFT, JPEG, HWT etc. Few of the most important properties of a DSP core watermarking process are as follows: (a) Low embedding cost (b) Secret mark (c) Low creation time (d) Strong tamper tolerance (e) Fault tolerance. [5] [6]

Contents

Process of hardware watermarking

Hardware or IP core watermarking in the context of DSP/Multimedia Cores are significantly different from watermarking of images/digital content. IP Cores are usually complex in size and nature and thus require highly sophisticated mechanisms to implant signatures within their design without disturbing the functionality. Any small change in the functionality of the IP core renders the hardware watermarking process futile. Such is the sensitivity of this process. Hardware Watermarking [7] [8] [9] can be performed in two ways: (a) Single-phase watermarking, (b) Multi-phase watermarking.

Single-phase watermarking process

As the name suggests, in single-phase watermarking process the secret marks in the form of additional constraints are inserted in a particular phase of design abstraction level. Among the all design abstraction level of Electronic design automation process inserting watermarking constraints at High-level synthesis is always beneficial, especially where the applications have complex algorithms (such as Digital signal processor, Media processor). The register allocation phase of High-level synthesis is one of the popular locations where single-phase watermarking constraints are inserted. Mostly the secret marks are inserted in the register allocation phase using the concept of Graph coloring, where each additional constraint is added as an additional edge of the graph. Moreover, the additional constraints are mapped with an encoded variable for providing another layer of security. In binary encoding process [2] the signature is provided in the form of 0 and 1; where each digit indicates a decoded constraints. In multi-variable encoding process [3] [7] the signature is provided in the form of four different variables viz. 'i', 'T', 'I', '!'.

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design.

High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior. Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from e.g. clock-level timing. Early HLS explored a variety of input specification languages., although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC/MATLAB. The code is analyzed, architecturally constrained, and scheduled to transcompile into a register-transfer level (RTL) design in a hardware description language (HDL), which is in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process.

Digital signal processor specialized microprocessor optimized for digital signal processing

A digital signal processor (DSP) is a specialized microprocessor, with its architecture optimized for the operational needs of digital signal processing.

Multi-phase watermarking process

As the name suggests, in the multi-phase watermarking process the additional constraints are inserted in multiple phases of a particular design abstraction level. For example, in High-level synthesis scheduling, hardware allocation and register allocation are used to insert a watermark. The main challenge of the multi-phase watermarking process is the dependence between additional constraints of multiple phases. In an ideal scenario, the watermarking constraints of each phase should not depend on each other. In other words, if somehow the watermarking constraints of a particular phase are tampered or removed, it should not impact the constraints of other phases. In multi-phase encoding process [1] [4] the signature is provided in the form of seven different variables viz. 'α', 'β', 'γ' 'i', 'T', 'I', '!'; where γ inserts watermark in scheduling phase, α and β insert watermark in hardware allocation phase, i, T, I, and ! insert watermark in the register allocation phase.

See also

Hardware obfuscation is a technique by which the description or the structure of electronic hardware is modified to intentionally conceal its functionality, which makes it significantly more difficult to reverse-engineer. In other words, hardware Obfuscation modifies the design in such a away that the resulting architecture becomes un-obvious to an adversary. Hardware Obfuscation can be of two types depending on the hardware platform targeted: (a) DSP Core Hardware Obfuscation - this type of obfuscation performs certain high level transformation on the data flow graph representation of DSP core to convert it into an unknown form that reflects an un-obvious architecture at RTL or gate level. This type of obfuscation is also called 'Structural Obfuscation'. Another type of DSP Core Obfuscation method is called 'Functional Obfuscation' - It uses a combination of AES and IP core locking blocks (ILBs) to lock the functionality of the DSP core using key-bits. Without application of correct key sequence, the DSP core produces either wrong output or no output at all (b) Combinational/Sequential Hardware Obfuscation - this type of obfuscation performs changes to the gate level structure of the circuit itself.

In electronic design a semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party. IP cores may be licensed to another party or can be owned and used by a single party alone. The term is derived from the licensing of the patent and/or source code copyright that exist in the design. IP cores can be used as building blocks within application-specific integrated circuit (ASIC) designs or field-programmable gate array (FPGA) logic designs.

Graph coloring assignment of labels traditionally called "colors" to elements of a graph

In graph theory, graph coloring is a special case of graph labeling; it is an assignment of labels traditionally called "colors" to elements of a graph subject to certain constraints. In its simplest form, it is a way of coloring the vertices of a graph such that no two adjacent vertices are of the same color; this is called a vertex coloring. Similarly, an edge coloring assigns a color to each edge so that no two adjacent edges are of the same color, and a face coloring of a planar graph assigns a color to each face or region so that no two faces that share a boundary have the same color.

Related Research Articles

Field-programmable gate array array of logic gates that are reprogrammable

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence the term "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an Application-Specific Integrated Circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools.

In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits.

System on a chip type of integrated circuit

A system on a chip is an integrated circuit that integrates all components of a computer or other electronic system. These components typically include a central processing unit (CPU), memory, input/output ports and secondary storage – all on a single substrate or microchip, the size of a coin. It may contain digital, analog, mixed-signal, and often radio frequency signal processing functions, depending on the application. As they are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are very common in the mobile computing and edge computing markets. Systems on chip are commonly used in embedded systems and the Internet of Things.

Application-specific integrated circuit Integrated circuit customized (typically optimized) for a specific task

An application-specific integrated circuit is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed to run in a digital voice recorder or a high-efficiency bitcoin miner is an ASIC. Application-specific standard products (ASSPs) are intermediate between ASICs and industry standard integrated circuits like the 7400 series or the 4000 series.

Digital watermarking

A digital watermark is a kind of marker covertly embedded in a noise-tolerant signal such as audio, video or image data. It is typically used to identify ownership of the copyright of such signal. "Watermarking" is the process of hiding digital information in a carrier signal; the hidden information should, but does not need to, contain a relation to the carrier signal. Digital watermarks may be used to verify the authenticity or integrity of the carrier signal or to show the identity of its owners. It is prominently used for tracing copyright infringements and for banknote authentication.

Direct digital synthesis

Direct digital synthesis (DDS) is a method employed by frequency synthesizers used for creating arbitrary waveforms from a single, fixed-frequency reference clock. DDS is used in applications such as signal generation, local oscillators in communication systems, function generators, mixers, modulators, sound synthesizers and as part of a digital phase-locked loop.

Integrated circuit design Engineering process for electronic hardware

Integrated circuit design, or IC design, is a subset of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography.

In VLSI semiconductor manufacturing, the process of Design Closure is a part of the development workflow by which an integrated circuit design is modified from its initial description to meet a growing list of design constraints and objectives.

The primary focus of this article is asynchronous control in digital electronic systems. In a synchronous system, operations are coordinated by one, or more, centralized clock signals. An asynchronous digital system, in contrast, has no global clock. Asynchronous systems do not depend on strict arrival times of signals or messages for reliable operation. Coordination is achieved via events such as: packet arrival, changes (transitions) of signals, handshake protocols, and other methods.

The asynchronous array of simple processors (AsAP) architecture comprises a 2-D array of reduced complexity programmable processors with small scratchpad memories interconnected by a reconfigurable mesh network. AsAP was developed by researchers in the VLSI Computation Laboratory (VCL) at the University of California, Davis and achieves high performance and energy-efficiency, while using a relatively small circuit area.

Cadence Design Systems American electronic design automation (EDA) software and engineering services company

Cadence Design Systems, Inc. is an American multinational electronic design automation (EDA) software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.

An application-specific instruction set processor (ASIP) is a component used in system-on-a-chip design. The instruction set of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose CPU and the performance of an ASIC.

Physical design (electronics)

In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called integrated circuit layout. This step is usually split into several sub-steps, which include both design and verification and validation of the layout.

A Hardware Trojan (HT) is a malicious modification of the circuitry of an integrated circuit. A hardware Trojan is completely characterized by its physical representation and its behavior. The payload of an HT is the entire activity that the Trojan executes when it is triggered. In general, malicious Trojans try to bypass or disable the security fence of a system: It can leak confidential information by radio emission. HT's also could disable, derange or destroy the entire chip or components of it.

Saraju Mohanty American academic

Saraju Mohanty is an American professor of the Department of Computer Science and Engineering, and the director of the Smart Electronic Systems Laboratory, at the University of North Texas in Denton, Texas. Mohanty received a Glorious India Award - Rich and Famous NRIs of America in 2017 for his contributions to the discipline. Mohanty is a researcher in the areas of "consumer electronics for smart cities", "application-Specific things for efficient edge computing", and "methodologies for digital and mixed-signal hardware". He has made significant research contributions to security and IP protection of consumer electronic systems, hardware-assisted security and protection, high-level synthesis of digital signal processing (DSP) hardware, and mixed-signal integrated circuit computer-aided design and electronic design automation. Mohanty has been the Editor-in-Chief (EiC) of the IEEE Consumer Electronics Magazine since 2016. He has held the Chair of the IEEE Computer Society's Technical Committee on Very Large Scale Integration since September 2014. He holds 4 US patents in the areas of his research, and has published 220 research articles and 3 books.

Technical Committee on VLSI (TCVLSI) is a constituency of IEEE Computer Society (IEEE-CS) that oversees various technical activities related to computer hardware, integrated circuit design, software for computer hardware design. TCVLSI is one of the 26 technical committees/councils of IEEE-CS that covers various specializations of computer science and computer engineering discipline. IEEE-CS is the largest of the 39 societies of Institute of Electrical and Electronics Engineers (IEEE). The technical scope of TCVLSI covers the Computer-aided design (CAD) or electronic design automation (EDA) techniques to facilitate the VLSI design process. The VLSI may include various types of circuits and systems, such as digital circuits and systems, analog circuits, as well as mixed-signal circuits and systems. The emphasis of TCVLSI widely covers the integrating the design, Computer-aided design (CAD), fabrication, application, and business aspects of Very-large-scale integration (VLSI) while encompassing both hardware and software.

References

  1. 1 2 Anirban Sengupta, Dipanjan Roy, Saraju P Mohanty, "Triple-Phase Watermarking for Reusable IP Core Protection during Architecture Synthesis", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Volume: 37, Issue: 4, April 2018, pp. 742 - 755
  2. 1 2 F. Koushanfar, I. Hong, and M. Potkonjak, “Behavioral synthesis techniques for intellectual property protection”, ACM Trans. Des. Autom. Electron. Syst., Vol. 10, No. 3, 2005, pp. 523-545
  3. 1 2 Anirban Sengupta, Dipanjan Roy "Anti-Piracy aware IP Chipset Design for CE Devices: Robust Watermarking Approach", IEEE Consumer Electronics, Volume: 6, Issue: 2, April 2017, pp. 118 - 124
  4. 1 2 Anirban Sengupta, Saumya Bhadauria, "Exploring Low Cost Optimal Watermark for Reusable IP Cores during High Level Synthesis", IEEE Access Journal, Volume:4, Issue: 99, pp. 2198 - 2215, May 2016
  5. ↑ Anirban Sengupta, Saumya Bhadauria "IP core Protection of CDFGs using Robust Watermarking during Behavioral Synthesis Based on User Resource Constraint and Loop Unrolling Factor", IET Electronics Letters, Vol. 52 No. 6 pp. 439-441, March 2016
  6. ↑ Anirban Sengupta, Dipanjan Roy "Automated Low Cost Scheduling Driven Watermarking Methodology for Modern CAD High-Level Synthesis Tools" Elsevier Journal of Advances in Engineering Software, Volume 110, August 2017, pp 26-33
  7. 1 2 Dipanjan Roy, Anirban Sengupta "Low Overhead Symmetrical Protection of Reusable IP Core using Robust Fingerprinting and Watermarking during High Level Synthesis", Elsevier Journal on Future Generation Computer Systems, Volume 71, June 2017, pp. 89–101
  8. ↑ Anirban Sengupta, Saumya Bhadauria, Saraju Mohanty "Embedding Low Cost Optimal Watermark During High Level Synthesis for Reusable IP Core Protection", Proc. of 48th IEEE Int'l Symposium on Circuits & Systems (ISCAS), Montreal, May 2016, pp. 974 - 977
  9. ↑ S. P. Mohanty, A. Sengupta, P. Guturu, and E. Kougianos, "Everything You Want to Know About Watermarking: From Paper Marks to Hardware Protection", IEEE Consumer Electronics, Volume 7, Issue 3, July 2017, pp. 83--91
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