M-PHY

Last updated
M-PHY
MIPI M-PHY
Year created2011
Created by MIPI Alliance
Supersedes D-PHY
Width in bits1–4 lanes, w/adaptive discovery (depending on higher-level protocol)
Speedup to 11.6 Gbit/s per data lane
Styleserial, embedded clock
External interfaceyes, with optical media converter
Website https://mipi.org/specifications/m-phy

M-PHY is a high speed data communications physical layer protocol standard developed by the MIPI Alliance, PHY Working group, and targeted at the needs of mobile multimedia devices. [1] The specification's details are proprietary to MIPI member organizations, but a substantial body of knowledge can be assembled from open sources. A number of industry standard settings bodies have incorporated M-PHY into their specifications including Mobile PCI Express, [2] [3] [4] [5] [6] [7] [8] Universal Flash Storage, [9] [10] [11] and as the physical layer for SuperSpeed InterChip USB. [12] [13] [14] [15] [16] [17]

Contents

To support high speed, M-PHY is generally transmitted using differential signaling over impedance controlled traces between components. When use on a single circuit card, the use of electrical termination may be optional. Options to extend its range could include operation over a short flexible flat cable, and M-PHY was designed to support optical media converters allowing extended distance between transmitters and receivers, and reducing concerns with electromagnetic interference. [15]

Applications

M-PHY (like its predecessor[ dubious ] D-PHY) is intended to be used in high-speed point-to-point communications, for example video Camera Serial Interfaces. The CSI-2 interface was based on D-PHY (or C-PHY), while the newer CSI-3 interface is based on M-PHY. M-PHY was designed to supplant D-PHY in many applications, but this is expected to take a number of years.

The M-PHY the physical layer is also used in a number of different high-speed emergent industry standards, DigRF (High speed radio interface), MIPI LLI (Low latency memory interconnect for multi-processors systems), and one possible physical layer for the UniPro protocol stack.

Signaling speed and gears

M-PHY supports a scalable variety of signaling speeds, ranging from 10 kbit/s to over 11.6 Gbit/s per lane. This is accomplished using two different major signaling/speed modes, a simple low-speed (using PWM) mode and high speed (using 8b10b). [18] Communications goes on in bursts, and the design of both high-speed and low-speed forms allows for extended periods of idle communications at low-power, making the design particularly suitable for mobile devices.

Within each signaling method, a number of standard speeds, known as "gears", is defined, with the expectation that additional gears will be defined in future versions of the standard. [19]

Related Research Articles

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References

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  5. "PCIe for Mobile Launched; PCIe 3.1, 4.0 Specs Revealed". 28 June 2013.
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  8. "MindShare - Mobile PCI Express (M-PCIe) (Training)". www.mindshare.com.
  9. "Universal Flash Storage (UFS) - JEDEC". www.jedec.org.
  10. "Universal Flash Storage: Mobilize Your Data". Design And Reuse.
  11. "UFS 3.0 standard released, offers 2x faster performance than UFS 2.1". www.fonearena.com.
  12. "MIPI Alliance and USB 3.0 Promoter Group Announce Availability of SuperSpeed USB Inter-Chip". Edn.com. 2012-06-20. Retrieved 2018-04-22.
  13. "MIPI M-Phy Testing Services". 29 May 2014.
  14. "MIPI M-PHY". mipi.org.
  15. 1 2 "MIPI™ MPHY - An introduction". Design And Reuse.
  16. "MIPI M-PHY takes center stage". Design And Reuse.
  17. "Specifications". eecatalog.com.
  18. MIPIAlliance (18 December 2012). "MIPI M-PHY Electrical Characterisation & Challenges by Parthasarathy Raju, Tektronix - part 1" via YouTube.
  19. MIPIAlliance (18 December 2012). "MIPI M-PHY Electrical Characterisation & Challenges by Parthasarathy Raju, Tektronix - part 1" via YouTube.