Mike Johnson (technologist)

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William Michael Johnson is a technologist, and pioneer in superscalar microprocessor design in the United States.

Johnson holds bachelor's and master's degrees in electrical engineering, both from Arizona State University. Johnson was an architect and designer of early reduced instruction set computing (RISC) processors at IBM known as ROMP, in Austin, Texas. [1] Johnson joined Advanced Micro Devices (AMD) in 1985 as the chief architect of the AMD Am29000 family (commonly known as "29K") of microprocessors. [2] He graduated with a Ph.D. in electrical engineering from Stanford University in 1989, working with Professor Mark Horowitz. [3] [4]

He held various management and leadership positions on the AMD K5 [5] and K7 processor teams. [6] [7] He was vice president of the Advanced Architecture Labs, responsible for technology development in the areas of processor, multimedia, networking, telecommunications, and personal computer system products. He was vice president of the AMD Personal Connectivity Solutions Group in 2002. [8] By 2004 he was a senior AMD fellow. [9]

Later he headed Texas Instruments' Austin Microprocessor Design Center. He helped organize a 2005 conference on revitalizing computer architecture research. [10] He served on the electrical engineering advisory council for Arizona State. [11]

Johnson wrote a seminal book on microprocessor superscalar architecture in 1991. The first book on the subject, it was an expanded version of his dissertation, and included an appendix on applying the techniques to the Intel Corporation x86 architecture. [5] He was quoted as saying: "The x86 really isn't all that complex—it just doesn't make a lot of sense." [5]

Selected works

Related Research Articles

A complex instruction set computer is a computer architecture in which single instructions can execute several low-level operations or are capable of multi-step operations or addressing modes within single instructions. The term was retroactively coined in contrast to reduced instruction set computer (RISC) and has therefore become something of an umbrella term for everything that is not RISC, where the typical differentiating characteristic is that most RISC designs use uniform instruction length for almost all instructions, and employ strictly separate load and store instructions.

<span class="mw-page-title-main">AMD K6</span> Computer microprocessor

The K6 microprocessor was launched by AMD in 1997. The main advantage of this particular microprocessor is that it was designed to fit into existing desktop designs for Pentium-branded CPUs. It was marketed as a product that could perform as well as its Intel Pentium II equivalent but at a significantly lower price. The K6 had a considerable impact on the PC market and presented Intel with serious competition.

<span class="mw-page-title-main">Pentium (original)</span> Intel microprocessor

The Pentium is a fifth generation, 32-bit x86 microprocessor that was introduced by Intel on March 22, 1993, as the very first CPU in the Pentium brand. It was instruction set compatible with the 80486 but was a new and very different microarchitecture design from previous iterations. The P5 Pentium was the first superscalar x86 microarchitecture and the world's first superscalar microprocessor to be in mass production—meaning it generally executes at least 2 instructions per clock mainly because of a design-first dual integer pipeline design previously thought impossible to implement on a CISC microarchitecture. Additional features include a faster floating-point unit, wider data bus, separate code and data caches, and many other techniques and features to enhance performance and support security, encryption, and multiprocessing, for workstations and servers when compared to the next best previous industry standard processor implementation before it, the Intel 80486.

<span class="mw-page-title-main">Reduced instruction set computer</span> Processor executing one instruction in minimal clock cycles

In computer science, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler to achieve given simpler instructions.

x86 Family of instruction set architectures

x86 is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introduced in 1978 as a fully 16-bit extension of Intel's 8-bit 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 and 80486 processors. Colloquially, their names were "186", "286", "386" and "486".

<span class="mw-page-title-main">Superscalar processor</span> CPU that implements instruction-level parallelism within a single processor

A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a superscalar processor can execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution units on the processor. It therefore allows more throughput than would otherwise be possible at a given clock rate. Each execution unit is not a separate processor, but an execution resource within a single CPU such as an arithmetic logic unit.

Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units mostly allow programs to specify instructions to execute in sequence only, a VLIW processor allows programs to explicitly specify instructions to execute in parallel. This design is intended to allow higher performance without the complexity inherent in some other designs.

NexGen, Inc. was a private semiconductor company based in Milpitas, California, that designed x86 microprocessors until it was purchased by AMD in 1996. NexGen was a fabless design house that designed its chips but relied on other companies for production. NexGen's chips were produced by IBM's Microelectronics division in Burlington, Vermont alongside PowerPC and DRAM parts.

<span class="mw-page-title-main">WinChip</span> Series of CPUs

The WinChip series was a low-power Socket 7-based x86 processor designed by Centaur Technology and marketed by its parent company IDT.

<span class="mw-page-title-main">AMD K5</span> Microarchitecture

The K5 is AMD's first x86 processor to be developed entirely in-house. Introduced in March 1996, its primary competition was Intel's Pentium microprocessor. The K5 was an ambitious design, closer to a Pentium Pro than a Pentium regarding technical solutions and internal architecture. However, the final product was closer to the Pentium regarding performance, although faster clock-for-clock compared to the Pentium.

<span class="mw-page-title-main">AMD Am29000</span> Family of RISC microprocessors and microcontrollers

The AMD Am29000, commonly shortened to 29k, is a family of 32-bit RISC microprocessors and microcontrollers developed and fabricated by Advanced Micro Devices (AMD). Based on the seminal Berkeley RISC, the 29k added a number of significant improvements. They were, for a time, the most popular RISC chips on the market, widely used in laser printers from a variety of manufacturers.

<span class="mw-page-title-main">History of general-purpose CPUs</span> History of processors used in general purpose computers

The history of general-purpose CPUs is a continuation of the earlier history of computing hardware.

<span class="mw-page-title-main">Mark Horowitz</span> American electrical engineer (1957–)

Mark A. Horowitz is an American electrical engineer, computer scientist, inventor, and entrepreneur who is the Yahoo! Founders Professor in the School of Engineering and the Fortinet Founders Chair of the Department of Electrical Engineering at Stanford University. He holds a joint appointment in the Electrical Engineering and Computer Science departments and previously served as the Chair of the Electrical Engineering department from 2008 to 2012. He is a co-founder of Rambus Inc., now a technology licensing company. Horowitz has authored over 700 published conference and research papers and is among the most highly-cited computer architects of all time. He is a prolific inventor and holds 374 patents as of 2023.

<span class="mw-page-title-main">Mark Papermaster</span> American business executive (born 1961)

Mark D. Papermaster is an American business executive currently serving as the chief technology officer (CTO) and executive vice president for Technology and Engineering at Advanced Micro Devices (AMD). On January 25, 2019 he was promoted to AMD's Executive Vice President. Papermaster previously worked at IBM from 1982 to 2008, where he was closely involved in the development of PowerPC technology and served two years as vice president of IBM's blade server division. Papermaster's decision to move from IBM to Apple Inc. in 2008 became central to a court case considering the validity and scope of an employee non-compete clause in the technology industry. He became senior vice president of devices hardware engineering at Apple in 2009, with oversight for devices such as the iPhone. In 2010 he left Apple and joined Cisco Systems as a VP of the company's silicon engineering development. Papermaster joined AMD on October 24, 2011, assuming oversight for all of AMD's technology teams and the creation of all of AMD's products, and AMD's corporate technical direction.

<span class="mw-page-title-main">Alpha 21264</span> RISC microprocessor

The Alpha 21264 is a Digital Equipment Corporation RISC microprocessor launched on 19 October 1998. The 21264 implemented the Alpha instruction set architecture (ISA).

A. Thampy Thomas is an electrical engineer who contributed to microprocessor pipeline architecture and founded semiconductor company NexGen microsystems.

Samuel Naffziger is an American electrical engineer who has been employed at Advanced Micro Devices in Fort Collins, Colorado since 2006. He was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2014 for his leadership in the development of power management and low-power processor technologies. He is also the Senior Vice President and Product Technology Architect at AMD.

References

  1. "VLSI systems design". Vol. 9, no. 1. CMP Publications. 1988. p. 8.
  2. Martin Marshall (November 28, 1988). "RISC: A fringe technology or the next rage in microcomputing?". InfoWorld. p. 46.
  3. W. M. Johnson (1989). Super-Scalar Processor Design (phd). Stanford University department of Electrical Engineering. Ph.D. dissertation.
  4. "VLSI Research Group: People". Stanford University. Archived from the original on September 2, 2011. Retrieved June 19, 2011.
  5. 1 2 3 Michael Slater (October 24, 1994). "AMD's K5 Designed to Outrun Pentium" (PDF). Microprocessor Report. Vol. 8, no. 14. MicroDesign Resources. Retrieved June 19, 2011.
  6. Brooke Crothers (February 20, 1995). "Intel enters SRAM market to support P6 design". InfoWorld. p. 10.
  7. Bob Guth; Terho Uimonen (October 2, 1995). "AMD's K5 faces another delay". InfoWorld. p. 20.
  8. "AMD Opens New Offices For Personal Connectivity Solutions Group". news release. Advanced Micro Devices. August 9, 2002. Retrieved June 19, 2011.
  9. "AMD And FASL LLC Join The MIPI Alliance To Develop And Promote Open Mobile Standards". news release. Advanced Micro Devices. February 18, 2004. Retrieved June 19, 2011.
  10. "Revitalizing Computer Architecture Research" (PDF). Computing Research Association. December 4, 2005. Retrieved June 19, 2011.
  11. "Department of Electrical Engineering" (PDF). Arizona State University Ira A. Fulton School of Engineering. December 4, 2005. p. 2. Archived from the original (PDF) on October 8, 2011. Retrieved September 15, 2006.