Offset binary

This article is about biased representations in general. For the excess-3 representation, see Shifted binary (code). For binary shifting, see Bit shifting.

Offset binary, ^[1] also referred to as excess-K, ^[1] excess-N, excess-e, ^{[2] [3]} excess code or biased representation, is a method for signed number representation where a signed number n is represented by the bit pattern corresponding to the unsigned number n+K, K being the biasing value or offset. There is no standard for offset binary, but most often the K for an n-bit binary word is K = 2ⁿ⁻¹ (for example, the offset for a four-digit binary number would be 2³=8). This has the consequence that the minimal negative value is represented by all-zeros, the "zero" value is represented by a 1 in the most significant bit and zero in all other bits, and the maximal positive value is represented by all-ones (conveniently, this is the same as using two's complement but with the most significant bit is inverted). It also has the consequence that in a logical comparison operation, one gets the same result as with a true form numerical comparison operation, whereas, in two's complement notation a logical comparison will agree with true form numerical comparison operation if and only if the numbers being compared have the same sign. Otherwise the sense of the comparison will be inverted, with all negative values being taken as being larger than all positive values.

The 5-bit Baudot code used in early synchronous multiplexing telegraphs can be seen as an offset-1 (excess-1) reflected binary (Gray) code.

One historically prominent example of offset-64 (excess-64) notation was in the floating point (exponential) notation in the IBM System/360 and System/370 generations of computers. The "characteristic" (exponent) took the form of a seven-bit excess-64 number (The high-order bit of the same byte contained the sign of the significand). ^[4]

The 8-bit exponent in Microsoft Binary Format, a floating point format used in various programming languages (in particular BASIC) in the 1970s and 1980s, was encoded using an offset-129 notation (excess-129).

The IEEE Standard for Floating-Point Arithmetic (IEEE 754) uses offset notation for the exponent part in each of its various formats of precision. Unusually however, instead of using "excess 2ⁿ⁻¹" it uses "excess 2ⁿ⁻¹ − 1" (i.e. excess-15, excess-127, excess-1023, excess-16383) which means that inverting the leading (high-order) bit of the exponent will not convert the exponent to correct two's complement notation.

Offset binary is often used in digital signal processing (DSP). Most analog to digital (A/D) and digital to analog (D/A) chips are unipolar, which means that they cannot handle bipolar signals (signals with both positive and negative values). A simple solution to this is to bias the analog signals with a DC offset equal to half of the A/D and D/A converter's range. The resulting digital data then ends up being in offset binary format. ^[5]

Most standard computer CPU chips cannot handle the offset binary format directly^{[ citation needed ]}. CPU chips typically can only handle signed and unsigned integers, and floating point value formats. Offset binary values can be handled in several ways by these CPU chips. The data may just be treated as unsigned integers, requiring the programmer to deal with the zero offset in software. The data may also be converted to signed integer format (which the CPU can handle natively) by simply subtracting the zero offset. As a consequence of the most common offset for an n-bit word being 2ⁿ⁻¹, which implies that the first bit is inverted relative to two's complement, there is no need for a separate subtraction step, but one simply can invert the first bit. This sometimes is a useful simplification in hardware, and can be convenient in software as well.

Table of offset binary for four bits, with two's complement for comparison: ^[6]

Decimal	Offset binary, K = 8	Two's complement
7	1111	0111
6	1110	0110
5	1101	0101
4	1100	0100
3	1011	0011
2	1010	0010
1	1001	0001
0	1000	0000
−1	0111	1111
−2	0110	1110
−3	0101	1101
−4	0100	1100
−5	0011	1011
−6	0010	1010
−7	0001	1001
−8	0000	1000

Offset binary may be converted into two's complement by inverting the most significant bit. For example, with 8-bit values, the offset binary value may be XORed with 0x80 in order to convert to two's complement. In specialised hardware it may be simpler to accept the bit as it stands, but to apply its value in inverted significance.

Related codes

${\displaystyle z={\frac {1}{q}}\left[\left(\sum _{i=1}^{n}p_{i}\times b_{i}\right)-k\right]}$ ^{[2] [3] [7]}

Code comparison ^{[2] [3] [7]}

Code	Type	Parameters			Weights	Distance	Checking	Complement	Groups of 5	Simple addition
		Offset, k	Width, n	Factor, q
8421 code	n [8]	0	4	1	8 4 2 1	1–4	No	No	No	No
Nuding code [8] [9]	3n + 2 [8]	2	5	3	N/A	2–5	Yes	9	Yes	Yes
Stibitz code [10]	n + 3 [8]	3	4	1	8  4 −2 −1	1–4	No	9	Yes	Yes
Diamond code [8] [11]	27n + 6 [8] [12] [13]	6	8	27	N/A	3–8	Yes	9	Yes	Yes
	25n + 15 [12] [13]	15	8	25	N/A	3+	Yes	Yes	?	Yes
	23n + 24 [12] [13]	24	8	23	N/A	3+	Yes	Yes	?	Yes
	19n + 42 [12] [13]	42	8	19	N/A	3–8	Yes	9	Yes	Yes

Decimal   0 1 2 3 4 5 6 7 8 9

8421 4 3 2 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1

Stibitz [10] 4 3 2 1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0

Nuding [8] [9] 5 4 3 2 1 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1

Diamond [8] 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 0 1 0 1 0 0 0 1 1 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 1

19n + 42 [12] [13] 8 7 6 5 4 3 2 1 0 0 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 1 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0 1 0 1 0 1

See also

• Signed number representations
• Binary number
• Excess-3
• Excess-128
• Exponent bias
• Excess-Gray code
• Ones' complement
• Binary offset carrier

References

1. Chang, Angela; Chen, Yen; Delmas, Patrice (2006-03-07). "2.5.2: Data Representation: Offset binary representation (Excess-K)". COMPSCI 210S1T 2006 (PDF). Department of Computer Science, The University of Auckland, NZ. p. 18. Retrieved 2016-02-04.
2. Dokter, Folkert; Steinhauer, Jürgen (1973-06-18). Digital Electronics. Philips Technical Library (PTL) / Macmillan Education (Reprint of 1st English ed.). Eindhoven, Netherlands: The Macmillan Press Ltd. / N. V. Philips' Gloeilampenfabrieken. p. 44. doi:10.1007/978-1-349-01417-0. ISBN   978-1-349-01419-4. SBN   333-13360-9 . Retrieved 2018-07-01. (270 pages) (NB. This is based on a translation of volume I of the two-volume German edition.)
3. Dokter, Folkert; Steinhauer, Jürgen (1975) [1969]. "2.4.4.4. Exzeß-e-Kodes". Digitale Elektronik in der Meßtechnik und Datenverarbeitung: Theoretische Grundlagen und Schaltungstechnik. Philips Fachbücher (in German). Vol. I (improved and extended 5th ed.). Hamburg, Germany: Deutsche Philips GmbH. pp. 51, 53–54. ISBN   3-87145-272-6. (xii+327+3 pages) (NB. The German edition of volume I was published in 1969, 1971, two editions in 1972, and 1975. Volume II was published in 1970, 1972, 1973, and 1975.)
4. IBM System/360 Principles of Operation Form A22-6821. Various editions available on the WWW.^{[ page needed ]}
5. Electrical and Computer Science Department, Southeastern Massachusetts University, North Dartmouth, MA, USA (1988). Chen, Chi-hau (ed.). Signal Processing Handbook. New York, USA: Marcel Dekker, Inc./CRC Press. ISBN   0-8247-7956-8 . Retrieved 2016-02-04.
6. "Data Conversion Binary Code Formats" (PDF). Intersil Corporation (published 2000). May 1997. AN9657.1. Retrieved 2016-02-04.
7. Morgenstern, Bodo (January 1997) [July 1992]. "10.5.3.5 Excess-e-Code". Elektronik: Digitale Schaltungen und Systeme. Studium Technik (in German). Vol. 3 (revised 2nd ed.). Friedrich Vieweg & Sohn Verlagsgesellschaft mbH. pp. 120–121. doi:10.1007/978-3-322-85053-9. ISBN   978-3-528-13366-5 . Retrieved 2020-05-26. (xviii+393 pages)
8. Diamond, Joseph M. (April 1955) [1954-11-12]. "Checking Codes for Digital Computers". Proceedings of the IRE . Correspondence. New York, USA. 43 (4): 483–490 [487–488]. doi:10.1109/JRPROC.1955.277858. eISSN   2162-6634. ISSN   0096-8390. Archived from the original on 2020-05-26. Retrieved 2020-05-26. (2 pages) (NB. The results discussed in this report are based on an earlier study carried out by Joseph M. Diamond and Morris Plotkin at Moore School of Engineering, University of Pennsylvania, in 1950–1951, on contract with the Burroughs Adding Machine Co.)
9. Nuding, Erich (1959-01-01). "Ein Sicherheitscode für Fernschreibgeräte, die zur Ein- und Ausgabe an elektronischen Rechenmaschine verwendet werden". Zeitschrift für Angewandte Mathematik und Mechanik. Kleine Mitteilungen (in German). 39 (5–6): 429. Bibcode:1959ZaMM...39..249N. doi:10.1002/zamm.19590390511. (1 page)
10. Stibitz, George Robert (1954-02-09) [1941-04-19]. "Complex Computer". Patent US2668661A. Retrieved 2020-05-24. (102 pages)
11. Plotkin, Morris (September 1960). "Binary Codes with Specified Minimum Distance". IRE Transactions on Information Theory . IT-6 (4): 445–450. doi:10.1109/TIT.1960.1057584. eISSN   2168-2712. ISSN   0096-1000. S2CID   40300278. (NB. Also published as Research Division Report 51-20 of University of Pennsylvania in January 1951.)
12. Brown, David T. (September 1960). "Error Detecting and Correcting Binary Codes for Arithmetic Operations". IRE Transactions on Electronic Computers . EC-9 (3): 333–337. doi:10.1109/TEC.1960.5219855. ISSN   0367-9950. S2CID   28263032.
13. Peterson, William Wesley; Weldon, Jr., Edward J. (1972) [February 1971, 1961]. "15.3 Arithmetic Codes / 15.6 Self-Complementing AN + B Codes". Written at Honolulu, Hawaii. Error-Correcting Codes (2 ed.). Cambridge, Massachusetts, USA: The Massachusetts Institute of Technology (The MIT Press). pp. 454–456, 460–461 [456, 461]. ISBN   0-262-16-039-0. LCCN   76-122262. (xii+560+4 pages)

Further reading

• Gosling, John B. (1980). "6.8.5 Exponent Representation". In Sumner, Frank H. (ed.). Design of Arithmetic Units for Digital Computers. Macmillan Computer Science Series (1 ed.). Department of Computer Science, University of Manchester, Manchester, UK: The Macmillan Press Ltd. pp. 91, 137. ISBN   0-333-26397-9. […] [w]e use a[n exponent] value which is shifted by half the binary range of the number. […] This special form is sometimes referred to as a biased exponent, since it is the conventional value plus a constant. Some authors have called it a characteristic, but this term should not be used, since CDC and others use this term for the mantissa. It is also referred to as an 'excess -' representation, where, for example, - is 64 for a 7-bit exponent (2⁷⁻¹ = 64). […]
• Savard, John J. G. (2018) [2006]. "Decimal Representations". quadibloc. Archived from the original on 2018-07-16. Retrieved 2018-07-16. (NB. Mentions Excess-3, Excess-6, Excess-11, Excess-123.)
• Savard, John J. G. (2018) [2007]. "Chen-Ho Encoding and Densely Packed Decimal". quadibloc. Archived from the original on 2018-07-03. Retrieved 2018-07-16. (NB. Mentions Excess-25, Excess-250.)
• Savard, John J. G. (2018) [2005]. "Floating-Point Formats". quadibloc. Archived from the original on 2018-07-03. Retrieved 2018-07-16. (NB. Mentions Excess-32, Excess-64, Excess-128, Excess-256, Excess-976, Excess-1023, Excess-1024, Excess-2048, Excess-16384.)
• Savard, John J. G. (2018) [2005]. "Computer Arithmetic". quadibloc. Archived from the original on 2018-07-16. Retrieved 2018-07-16. (NB. Mentions Excess-64, Excess-500, Excess-512, Excess-1024.)