Simple Bus Architecture

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SBA Master code example Master code example.png
SBA Master code example
SBA Master IP Core Interface Interfaz Maestro.png
SBA Master IP Core Interface
SBA Slave IP Core Interface Interfaz Esclavo.png
SBA Slave IP Core Interface
SBA Address Space IP Core Interface Interfaz Address Space.png
SBA Address Space IP Core Interface
SBA basic block diagram SBA BusDiagram v2.png
SBA basic block diagram

The Simple Bus Architecture [1] (SBA) is a form of computer architecture. It is made up software tools and intellectual property cores (IP Core) interconnected by buses using simple and clear rules, that allow the implementation of an embedded system (SoC). Basic templates are provided to accelerate design. The VHDL code that implements this architecture is portable.

Computer architecture set of rules and methods that describe the functionality, organization, and implementation of computer systems

In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems. Some definitions of architecture define it as describing the capabilities and programming model of a computer but not a particular implementation. In other definitions computer architecture involves instruction set architecture design, microarchitecture design, logic design, and implementation.

Software non-tangible executable component of a computer

Computer software, or simply software, is a collection of data or computer instructions that tell the computer how to work. This is in contrast to physical hardware, from which the system is built and actually performs the work. In computer science and software engineering, computer software is all information processed by computer systems, programs and data. Computer software includes computer programs, libraries and related non-executable data, such as online documentation or digital media. Computer hardware and software require each other and neither can be realistically used on its own.

Intellectual property (IP) is a category of property that includes intangible creations of the human intellect. Intellectual property encompasses two types of rights; industrial property rights and copyright. It was not until the 19th century that the term "intellectual property" began to be used, and not until the late 20th century that it became commonplace in the majority of the world.

Master core

The master core is a finite state machine (FSM) and performs basic data flow and processing, similar to a microprocessor, but with lower consumption of logic resources. One possible way to implement FSMs is to have a controller that acts as a switch box. When the thread of execution executes FSM code, it runs the controller that evaluates/determines the current state, usually through the use of a switch (case) statement or if-then-else statements. Once the current state is determined, its code is executed, performing actions and setting the state transitions for the next FSM execution. The controller may be a simple switch statement, but an implementation may have the controller perform pre-processing of inputs and triggering of state transitions before-hand.

Microprocessor computer processor contained on an integrated-circuit chip

A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC), or at most a few integrated circuits. The microprocessor is a multipurpose, clock driven, register based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, and provides results as output. Microprocessors contain both combinational logic and sequential digital logic. Microprocessors operate on numbers and symbols represented in the binary number system.

Wishbone

SBA is an application and a simplified version of the Wishbone [2] specification. SBA implements the minimum essential subset of the Wishbone signals interface. It can be connected with simple Wishbone IP Cores. SBA defines three types of cores: masters, slaves, and auxiliaries. Several slave IP Cores were developed following the SBA architecture, many to implement virtual instruments.

Wishbone (computer bus) computer bus

The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip. The Wishbone Bus is used by many designs in the OpenCores project.

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In computer science, an interpreter is a computer program that directly executes, i.e. performs instructions written in a programming or scripting language, without requiring them previously to have been compiled into a machine language program. An interpreter generally uses one of the following strategies for program execution:

  1. parse the source code and perform its behavior directly;
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Preboot Execution Environment Preboot Execution Environment

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Profibus communications protocol

PROFIBUS is a standard for fieldbus communication in automation technology and was first promoted in 1989 by BMBF and then used by Siemens. It should not be confused with the PROFINET standard for Industrial Ethernet. PROFIBUS is openly published as part of IEC 61158.

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Microarchitecture the way a given instruction set architecture (ISA) is implemented on a processor

In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA), is implemented in a particular processor. A given ISA may be implemented with different microarchitectures; implementations may vary due to different goals of a given design or due to shifts in technology.

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The MicroBlaze is a soft microprocessor core designed for Xilinx field-programmable gate arrays (FPGA). As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.

The ARM Advanced Microcontroller Bus Architecture (AMBA) is an open-standard, on-chip interconnect specification for the connection and management of functional blocks in system-on-a-chip (SoC) designs. It facilitates development of multi-processor designs with large numbers of controllers and peripherals with a bus architecture. Since its inception, the scope of AMBA has, despite its name, gone far beyond microcontroller devices. Today, AMBA is widely used on a range of ASIC and SoC parts including applications processors used in modern portable mobile devices like smartphones. AMBA is a registered trademark of ARM Ltd.

Kermeta is a modeling and programming language for metamodel engineering.

OpenRISC 1200

The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture.

Sercos III is the third generation of the Sercos interface, a globally standardized open digital interface for the communication between industrial controls, motion devices, input/output devices (I/O), and Standard Ethernet nodes. Sercos III merges the hard real-time aspects of the Sercos interface with Ethernet. It is based upon and conforms to the Ethernet standard. Work began on Sercos III in 2003, with vendors releasing first products supporting it in 2005. In addition to the standard Sercos features cited under the Sercos interface general description, Sercos III also provides:

The Media Gateway Control Protocol (MGCP) is a signaling and call control communications protocol used in voice over IP (VoIP) telecommunication systems. It implements the media gateway control protocol architecture for controlling media gateways on Internet Protocol (IP) networks connected to the public switched telephone network (PSTN). The protocol is a successor to the Simple Gateway Control Protocol (SGCP), which was developed by Bellcore and Cisco, and the Internet Protocol Device Control (IPDC).

UML state machine, also known as UML statechart, is a significantly enhanced realization of the mathematical concept of a finite automaton in computer science applications as expressed in the Unified Modeling Language (UML) notation.

Communications Processor Module (CPM) is a component of Motorola 68000 family (QUICC) or Motorola/Freescale Semiconductor Power Architecture (PowerQUICC) microprocessors designed to provide features related to imaging and communications. A microprocessor can delegate most of the input/output processing to the Communications Processor Module and the microprocessor does not have to perform those functions itself. Some input/output functions require quick response from the processor, for example due to precise timing requirements during data transmission. With CPM performing those operations, the main microprocessor is free to perform other tasks.

Media gateway control protocol architecture

The media gateway control protocol architecture is a methodology of providing telecommunication services using decomposed multimedia gateways for transmitting telephone calls between an Internet Protocol network and traditional analog facilities of the public switched telephone network (PSTN). The architecture was originally defined in RFC 2805 and has been used in several prominent voice over IP (VoIP) protocol implementations, such as the Media Gateway Control Protocol (MGCP) and Megaco (H.248), both successors to the obsolete Simple Gateway Control Protocol (SGCP).

Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. The Apollo Lake platform with 14 nm Goldmont core was unveiled at the Intel Developer Forum (IDF) in Shenzhen, China, April 2016. The Goldmont architecture borrows heavily from the Skylake Core processors, so it offers a more than 30 percent performance boost compared to the previous Braswell platform, and it can be used to implement power-efficient low-end devices including Cloudbooks, 2-in-1 netbooks, small PCs, IP cameras, and in-car entertainment systems.

References

  1. ↑ "SBA - Simple Bus Architecture". Sba.accesus.com. Retrieved 2014-05-15.
  2. ↑ OpenCores. (2011) “Wishbone, Revision B.4 Specification


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