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Double Data Rate Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR SDRAM, is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by DDR2 SDRAM, DDR3 SDRAM, and DDR4 SDRAM, which has since been superseded by DDR5 SDRAM. None of its successors are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, DDR4 and DDR5 memory modules will not work in DDR1-equipped motherboards, and vice versa.
Static random-access memory is a type of random-access memory (RAM) that uses latching circuitry (flip-flop) to store each bit. SRAM is volatile memory; data is lost when power is removed.
Dynamic random-access memory is a type of random-access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The electric charge on the capacitors slowly leaks off, so without intervention the data on the chip would soon be lost. To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory, since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.
Synchronous dynamic random-access memory is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.
Rambus DRAM (RDRAM), and its successors Concurrent Rambus DRAM (CRDRAM) and Direct Rambus DRAM (DRDRAM), are types of synchronous dynamic random-access memory (SDRAM) developed by Rambus from the 1990s through to the early-2000s. The third-generation of Rambus DRAM, DRDRAM was replaced by XDR DRAM. Rambus DRAM was developed for high-bandwidth applications, and was positioned by Rambus as replacement for various types of contemporary memories, such as SDRAM.
Double Data Rate 2 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR2 SDRAM, is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DDR3 SDRAM. DDR2 DIMMs are neither forward compatible with DDR3 nor backward compatible with DDR.
Magnetoresistive random-access memory (MRAM) is a type of non-volatile random-access memory which stores data in magnetic domains. Developed in the mid-1980s, proponents have argued that magnetoresistive RAM will eventually surpass competing technologies to become a dominant or even universal memory. Currently, memory technologies in use such as flash RAM and DRAM have practical advantages that have so far kept MRAM in a niche role in the market.
Rambus Incorporated, founded in 1990, is an American technology company that designs, develops and licenses chip interface technologies and architectures that are used in digital electronics products. The company is well known for inventing RDRAM and for its intellectual property-based litigation following the introduction of DDR-SDRAM memory.
Double Data Rate 3 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR3 SDRAM, is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors.
Memory bandwidth is the rate at which data can be read from or stored into a semiconductor memory by a processor. Memory bandwidth is usually expressed in units of bytes/second, though this can vary for systems with natural data sizes that are not a multiple of the commonly used 8-bit bytes.
GDDR4 SDRAM, an abbreviation for Graphics Double Data Rate 4 Synchronous Dynamic Random-Access Memory, is a type of graphics card memory (SGRAM) specified by the JEDEC Semiconductor Memory Standard. It is a rival medium to Rambus's XDR DRAM. GDDR4 is based on DDR3 SDRAM technology and was intended to replace the DDR2-based GDDR3, but it ended up being replaced by GDDR5 within a year.
GDDR5 SDRAM, an abbreviation for Graphics Double Data Rate 5 Synchronous Dynamic Random-Access Memory, is a modern type of synchronous graphics random-access memory (SGRAM) with a high bandwidth interface designed for use in graphics cards, game consoles, and high-performance computing. It is a type of GDDR SDRAM.
Elpida Memory, Inc. was a corporation established in 1999 that developed, designed, manufactured and sold dynamic random-access memory (DRAM) products. It was also a semiconductor foundry. With headquarters in Yaesu, Chūō, Tokyo, Japan, it was initially formed under the name NEC Hitachi Memory in 1999 by the merger of the Hitachi and NEC DRAM businesses. In the following year it took on the name Elpida. In 2003, Elpida took over the Mitsubishi DRAM business. In 2004, it listed its shares in the first section of the Tokyo Stock Exchange. In 2012, those shares were delisted as a result of its bankruptcy. In 2013, Elpida was acquired by Micron Technology.
The Open NAND Flash Interface Working Group, is a consortium of technology companies working to develop open standards for NAND flash memory and devices that communicate with them. The formation of ONFI was announced at the Intel Developer Forum in March 2006.
Double Data Rate 4 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR4 SDRAM, is a type of synchronous dynamic random-access memory with a high bandwidth interface.
Random-access memory is a form of computer memory that can be read and changed in any order, typically used to store working data and machine code. A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory. In contrast, with other direct-access data storage media such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory, the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.
GDDR3 SDRAM is a type of DDR SDRAM specialized for graphics processing units (GPUs) offering less access latency and greater device bandwidths. Its specification was developed by ATI Technologies in collaboration with DRAM vendors including Elpida Memory, Hynix Semiconductor, Infineon and Micron. It was later adopted as a JEDEC standard.
Hybrid Memory Cube (HMC) is a high-performance RAM interface for through-silicon vias (TSV)-based stacked DRAM memory competing with the incompatible rival interface High Bandwidth Memory (HBM).
High Bandwidth Memory (HBM) is a high-speed computer memory interface for 3D-stacked SDRAM from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerators, network devices and in some supercomputers. The first HBM memory chip was produced by SK Hynix in 2013, and the first devices to use HBM were the AMD Fiji GPUs in 2015.
3D XPoint is a non-volatile memory (NVM) technology developed jointly by Intel and Micron Technology. It was announced in July 2015 and is available on the open market under the brand name Optane (Intel) since April 2017. Bit storage is based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Initial prices are less than dynamic random-access memory (DRAM) but more than flash memory.
References
- 1 2 Jacob, Bruce et al. (2008). Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann Publishers. pp. 494.
- ↑ RLDRAM Memory: Unparalleled Bandwidth and Low Latency
- ↑ Infineon and Micron Announce RLDRAM II Specification
- ↑ Xilinx and Micron demo interoperability of FPGA and RLDRAM 3 memory interface standard