Mentor Graphics is a US-based electronic design automation (EDA) multinational corporation for electrical engineering and electronics, headquartered in Wilsonville, Oregon. Founded in 1981, the company was acquired by Siemens in 2017. Since 2021, the former Mentor Graphics operates as a division at Siemens named Siemens EDA.
Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to integrated circuits (ICs).
Synopsys is an American electronic design automation company that focuses on silicon design and verification, silicon intellectual property and software security and quality. Products include logic synthesis, behavioral synthesis, place and route, static timing analysis, formal verification, hardware description language simulators, and transistor-level circuit simulation. The simulators include development and debugging environments that assist in the design of the logic for chips and computer systems. In recent years, Synopsys has expanded its products and services to include application security testing. Their technology is present in self-driving cars, artificial intelligence, and internet of things consumer products.
Magma Design Automation was a software company in the electronic design automation (EDA) industry. The company was founded in 1997 and maintained headquarters in San Jose, California, with facilities throughout North America, Europe, Japan, Asia and India. Magma software products were used in major elements of Integrated circuit design, including: synthesis, placement, routing, power management, circuit simulation, verification and analog/mixed-signal design.
Silvaco Inc. develops and markets electronic design automation (EDA) and technology CAD (TCAD) software and semiconductor design IP (SIP). The company is headquartered in Santa Clara, California, and has a global presence with offices located in North America, Europe, and throughout Asia. Since its founding in 1984, Silvaco has grown to become a large privately held EDA company. The company has been known by at least two other names: Silvaco International, and Silvaco Data Systems.
VLSI Technology, Inc., was an American company that designed and manufactured custom and semi-custom integrated circuits (ICs). The company was based in Silicon Valley, with headquarters at 1109 McKay Drive in San Jose. Along with LSI Logic, VLSI Technology defined the leading edge of the application-specific integrated circuit (ASIC) business, which accelerated the push of powerful embedded systems into affordable products.
In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation. Cell-based methodology — the general class to which standard cells belong — makes it possible for one designer to focus on the high-level aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard cell methodology has helped designers scale ASICs from comparatively simple single-function ICs, to complex multi-million gate system-on-a-chip (SoC) devices.
Static timing analysis (STA) is a simulation method of computing the expected timing of a digital circuit without requiring a simulation of the full circuit.
OrCAD Systems Corporation was a software company that made OrCAD, a proprietary software tool suite used primarily for electronic design automation (EDA). The software is used mainly by electronic design engineers and electronic technicians to create electronic schematics, perform mixed-signal simulation and electronic prints for manufacturing printed circuit boards. OrCAD was taken over by Cadence Design Systems in 1999 and was integrated with Cadence Allegro since 2005.
Integrated circuit design, or IC design, is a sub-field of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography.
Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and wire.
The Si2 Common Power Format, or CPF is a file format for specifying power-saving techniques early in the design process. In the design of integrated circuits, saving power is a primary goal, and designers are forced to use sophisticated techniques such as clock gating, multi-voltage logic, and turning off the power entirely to inactive blocks. These techniques require a consistent implementation in the design steps of logic design, implementation, and verification. For example, if multiple different power supplies are used, then logic synthesis must insert level shifters, place and route must deal with them correctly, and other tools such as static timing analysis and formal verification must understand these components. As power became an increasingly pressing concern, each tool independently added the features needed. Although this made it possible to build low power flows, it was difficult and error prone since the same information needed to be specified several times, in several formats, to many different tools. CPF was created as a common format that many tools can use to specify power-specific data, so that power intent only need be entered once and can be used consistently by all tools. The aim of CPF is to support an automated, power-aware design infrastructure.
Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, in recent years the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. This has led to considerable research into statistical static timing analysis, which replaces the normal deterministic timing of gates and interconnects with probability distributions, and gives a distribution of possible circuit outcomes rather than a single outcome.
Cadence Design Systems, Inc., headquartered in San Jose, California, is an American multinational computational software company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital system and find a register-transfer level structure that realizes the given behavior.
Sigrity, acquired by Cadence Design Systems in 2012 for $80M.[1][2], supplies software for IC package physical design and for analyzing power integrity, signal integrity and design stage electromagnetic interference (EMI). Analysis is performed on chips, IC packages and printed circuit boards.
Solido Design Automation Inc. is an electronic design automation (EDA) software company, headquartered in Saskatoon, Saskatchewan. The company develops software for analog/mixed-signal and custom integrated circuits. The company was founded in 2005 and is funded by BDC Venture Capital, Victoria Park Capital, and Golden Opportunities Fund.
In the automated design of integrated circuits, signoff checks is the collective name given to a series of verification steps that the design must pass before it can be taped out. This implies an iterative process involving incremental fixes across the board using one or more check types, and then retesting the design. There are two types of sign-off's: front-end sign-off and back-end sign-off. After back-end sign-off the chip goes to fabrication. After listing out all the features in the specification, the verification engineer will write coverage for those features to identify bugs, and send back the RTL design to the designer. Bugs, or defects, can include issues like missing features, errors in design, etc. When the coverage reaches a maximum% then the verification team will sign it off. By using a methodology like UVM, OVM, or VMM, the verification team develops a reusable environment. Nowadays, UVM is more popular than others.
NanGate, Inc was a privately held US/Silicon Valley-based multinational corporation dealing in Electronic Design Automation (EDA) for electrical engineering and electronics until its acquisition by Silvaco, Inc. in 2018. NanGate was founded in October 2004 by a group of semiconductor professionals with a background from Intel Corporation and Vitesse Semiconductor Corp. The company has received capital investments from a group of Danish business angels and venture capital companies. The company is today owned and controlled by its management following a management buy-out in 2012. NanGate markets a range of software products and design services for the design and optimization of standard cell libraries and application-specific integrated circuits. The market focus is standard cell library design and optimization for 14-28 nanometer CMOS processes.
Lawrence Pileggi is the Tanoto Professor and Department Head of Electrical and Computer Engineering at Carnegie Mellon University. He is a specialist in the automation of integrated circuits, and developing software tools for the optimization of power grids. Pileggi’s research has been cited thousands of times in engineering papers.
