Bellmac 32

Last updated

The Bellmac 32 is a microprocessor developed by Bell Labs' processor division in 1980, implemented using CMOS technology and was the first microprocessor that could move 32 bits in one clock cycle. The microprocessor contains 150,000 transistors and improved on the speed of CMOS design by using "domino circuits". It was designed with the C programming language in mind. After its creation, an improved version was produced called the Bellmac 32A, then cancelled along with its successor, the "Hobbit" C-language Reduced Instruction Set Processor (CRISP).

Contents

History

The Bellmac 32 processor was developed by AT&T engineers in three different Bell Labs locations: Indian Hill, Holmdel and Murray Hill. [1]

As the designers did not have automation tools, every chip designer had to use colored pencils for the completion of the initial design. [1] Later, Steve Law developed a computer program that aided in the digitization of the initial designs.

The development of the Bellmac 32 produced a novel circuit design technique called domino logic , deemed a breakthrough for the production of the microprocessor. Tests performed during manufacture indicated that a clock frequency even higher than the 4 MHz target speed was possible. Implementing the control logic, however, proved unexpectedly complicated. These complications limited the final speed, when the entire chip was finished and tested, to 2 MHz. [1] The team considered it as progress, but not as successful, as it could not meet the initial AT&T design goals.

Followup design meetings resulted in the Bellmac 32A project, as a second generation of the Bellmac microprocessor. The project once again selected CMOS technology and fixed the target clock frequency at 6.2 MHz. Adjustments to maximize the size of transistors and resistors and minimizing interconnections were fundamental in meeting the specifications. The engineers placed a 20-foot-by-20-foot engineering drawing of the chip layout on the floor of a large room. [2] Testing of chips produced from the completed circuit exceeded the design speed, and reached clock frequencies of 7, 8, and even 9 MHz. [1]

After the breakup of AT&T, Bell Labs became a component of Western Electric. With this change, the Bellmac 32 was renamed to WE 32000. Updated versions of the chip included the WE 32100, announced in June 1984, [3] and the WE 32200.

Architecture

The Bellmac 32 has a pipelined architecture with an instruction fetch unit that serves to control access to main memory, and an execution unit which serves to monitor the process and manipulate data.

The instruction queue is filled with the instructions fetched from the memory. The address arithmetic unit serves for address calculations.

Programming language support

The Bellmac 32 architecture provides a variety of conveniences for programming language implementers. Procedure invocation involves the manipulation of four registers – the program counter, stack pointer, frame pointer and argument pointer – to transfer control between program procedures, along with use of the program stack to preserve register contents and communicate arguments and return values. Four instructions are offered to support such "procedure linkage": call saves the return address and argument pointer to the stack, save preserves selected registers in the range from R3 to R8 inclusive, restore restores any previously saved registers, and return obtains the stack frame prior to invocation and returns control to the saved return address. Addressing modes are provided that offer stack access relative to the argument pointer and frame pointer. [4]

Process management

The architecture supports a particular model of process management, where a process employs a single execution stack, and where a Process Control Block (PCB) retains the execution context of each process, holding copies of the process's register values along with "block move" data describing a process's virtual memory configuration. As a convenience for operating system implementers, architectural support for process switching includes two dedicated instructions analogous to the traditional jump-to-subroutine and return-from-subroutine instructions. The call-process instruction saves user and control registers to a given process's PCB via the privileged Process Control Block Pointer (PCBP) register, thus capturing the execution state of the current process and allowing it to be suspended, followed by the loading of such registers from another process's PCB, thus restoring the execution state of a given process. Meanwhile, the return-to-process instruction merely loads process state from a given PCB. By performing "block moves", the process switching instructions are able to automatically reconfigure the active virtual memory layout without further intervention by the operating system, and combining this reconfiguration with updates to the processor registers, these instructions permit the execution environment of process to be conveniently restored. [4]

Interrupt handling

Alongside the PCBP register, the Interrupt Stack Pointer (ISP) register is used to refer to a position on a common interrupt stack, used to record PCB pointers referencing the stored state of interrupted processes. When an interrupt is delivered, the dedicated call-process instruction is employed to suspend the running process, whose PCB address is stored on the interrupt stack, and to switch to an interrupt handler selected from a table. Interrupts behave like separate processes and are therefore provided with their own distinct execution stack. After interrupt handling is completed, the return-to-process instruction is then used to resume the suspended process. The selection of a suitable interrupt handler involves a table of PCB pointers in a fixed virtual memory location. [4]

Privileges, system calls and exception handling

Four privilege levels are supported by the Bellmac 32 architecture. To switch between privilege levels, the "controlled transfer" mechanism is provided, relying on a two-level table hierarchy to define the privilege level using the Processor Status Word (PSW) register and the location of each procedure or handler to be invoked by a "controlled call", thus providing a system call mechanism. Exception handling employs this controlled call mechanism to direct execution to an appropriate handler, which for a "normal" exception is found via a particular second-level table whose entries each correspond to a particular Internal State Code (ISC), defined in the PSW register. For the exception-related features of the Bellmac 32 to function, an operating system kernel is also expected to reside in each process's virtual address space since an exception, relying on a controlled transfer, will not change the virtual memory configuration. [4]

Instructions supporting the C language

Although various operations provided by the Bellmac 32 architecture support high-level languages generally, specific instructions are provided that support C language conventions, notably the string copy and string end instructions which rely on the C language representation of terminating character strings with a zero byte. A general block copy operation is also provided that utilises an explicit block length parameter to define the amount of data to be copied between locations. [4]

Registers

WE 32100 registers
31...23...15...07...00(bit position)
General registers
R0Register 0
R1Register 1
R2Register 2
R3Register 3
R4Register 4
R5Register 5
R6Register 6
R7Register 7
R8Register 8
R9 / FPFrame Ptr
R10 / APArgument Ptr
R11 / PSW (See below)Processor Status Word
R12 / SPStack Ptr
R13 / PCBPProcess Control Bock Ptr
R14 / ISPInterrupt Stack Ptr
R15 / PCProgram Counter

Bellmac 32 has sixteen 32-bit registers. Three of these (ISP, PCBP, PSW) are privileged, used to support the operating system and can be written only when the microprocessor is in kernel mode. There are three other registers (SP, AP, FP) that are used by some instructions as stack pointers. Execution level, set in the Processor Status Word, can be one of four states: Kernel, Executive, Supervisor, User. [5]

There are an additional sixteen registers in the WE 32200, [6] these being divided into two groups of eight registers: R16 to R23 being user registers, readable and writable in any processor mode, being intended for global variable and temporary storage; R24 to R31 being kernel, or privileged, registers that are only writable in kernel mode, being readable in any other mode. These additional registers were introduced to allow high-level language compilers to generate code that could use them to store frequently used data, thus improving the execution performance of such languages. [7]

Processor status word

Processor Status Word
31...2625242322212019181716...1312111009080706...03020100(bit position)
UnusedCFDQIECDOENZVCTEIPLCMPMRIISCTMETPSW

The Process Status Word is part of the register file and is aliased as R11.

BitsMeaning
31:26Unused
25Cache Flush Disable
24Quick-Interrupt Enable
23Cache Disable
22Enable Overflow Trap
21 Negative
20 Zero
19 Overflow
18 Carry
17Trace Enable
16:13Interrupt Priority Level
12:11Current Execution Level
10:9Previous Execution Level
8:7Register-Initial Context
6:3Internal State Code
2Trace Mask
1:0Exception Type

Instructions

This microprocessor has 169 instructions, which are optimized for executing programs written in the C programming language. Accordingly, the format of character strings is adapted to C language specifications, for example.

The instructions may have up to three operands. The processor has no floating-point or decimal arithmetic instructions, which were later provided by coprocessors WE 32106 and WE 32206.

Memory

The Bellmac 32 implements multiple types of memory addressing, such as linear, immediate 8, 16 or 32 bits, registration, register indirect, short shift, absolute and indirect displacement of 8, 16 or 32 bits.

Usage

The WE 32x00 processors were used in the AT&T Computer Systems' 3B series computers, being unveiled as commercially available products in the form of the 3B2, 3B5 and 3B20 ranges at the spring 1984 Comdex show. [8] In mid-1985, AT&T started to offer the WE 32100 and associated chipset, along with "board-level" evaluation systems, to other manufacturers. [9]

Supporting chips

AT&T had a lineup of WE 32x00 supporting chips and peripherals, [6] including:

Related Research Articles

In computing, a context switch is the process of storing the state of a process or thread, so that it can be restored and resume execution at a later point, and then restoring a different, previously saved, state. This allows multiple processes to share a single central processing unit (CPU), and is an essential feature of a multiprogramming or multitasking operating system. In a traditional CPU, each process - a program in execution - utilizes the various CPU registers to store data and hold the current state of the running process. However, in a multitasking operating system, the operating system switches between processes or threads to allow the execution of multiple processes simultaneously. For every switch, the operating system must save the state of the currently running process, followed by loading the next process state, which will run on the CPU. This sequence of operations that stores the state of the running process and the loading of the following running process is called a context switch.

<span class="mw-page-title-main">Intel 8080</span> 8-bit microprocessor

The Intel 8080 ("eighty-eighty") is the second 8-bit microprocessor designed and manufactured by Intel. It first appeared in April 1974 and is an extended and enhanced variant of the earlier 8008 design, although without binary compatibility. The initial specified clock rate or frequency limit was 2 MHz, with common instructions using 4, 5, 7, 10, or 11 cycles. As a result, the processor is able to execute several hundred thousand instructions per second. Two faster variants, the 8080A-1 and 8080A-2, became available later with clock frequency limits of 3.125 MHz and 2.63 MHz respectively. The 8080 needs two support chips to function in most applications: the i8224 clock generator/driver and the i8228 bus controller. It is implemented in N-type metal–oxide–semiconductor logic (NMOS) using non-saturated enhancement mode transistors as loads thus demanding a +12 V and a −5 V voltage in addition to the main transistor–transistor logic (TTL) compatible +5 V.

<span class="mw-page-title-main">Intel 8086</span> 16-bit microprocessor

The 8086 is a 16-bit microprocessor chip designed by Intel between early 1976 and June 8, 1978, when it was released. The Intel 8088, released July 1, 1979, is a slightly modified chip with an external 8-bit data bus, and is notable as the processor used in the original IBM PC design.

i386 32-bit microprocessor by Intel

The Intel 386, originally released as 80386 and later renamed i386, is a 32-bit microprocessor introduced in 1985. The first versions had 275,000 transistors and were the central processing unit (CPU) of many workstations and high-end personal computers of the time.

MIPS is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.

<span class="mw-page-title-main">Motorola 68000</span> Microprocessor

The Motorola 68000 is a 16/32-bit complex instruction set computer (CISC) microprocessor, introduced in 1979 by Motorola Semiconductor Products Sector.

<span class="mw-page-title-main">Motorola 6809</span> 8-bit microprocessor

The Motorola 6809 ("sixty-eight-oh-nine") is an 8-bit microprocessor with some 16-bit features. It was designed by Motorola's Terry Ritter and Joel Boney and introduced in 1978. Although source compatible with the earlier Motorola 6800, the 6809 offered significant improvements over it and 8-bit contemporaries like the MOS Technology 6502, including a hardware multiplication instruction, 16-bit arithmetic, system and user stack registers allowing re-entrant code, improved interrupts, position-independent code and an orthogonal instruction set architecture with a comprehensive set of addressing modes.

x86 Family of instruction set architectures

x86 is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introduced in 1978 as a fully 16-bit extension of Intel's 8-bit 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 and 80486 processors. Colloquially, their names were "186", "286", "386" and "486".

The NS32000, sometimes known as the 32k, is a series of microprocessors produced by National Semiconductor. The first member of the family came to market in 1982, briefly known as the 16032 before becoming the 32016. It was the first general-purpose microprocessor on the market that used 32-bit data throughout: the Motorola 68000 used 32-bit data but had a 16-bit ALU and thus took twice as long perform many operations. However, the 32016 contained many bugs and often could not be run at its rated speed. These problems, and the presence of the otherwise similar 68000 which had been available since 1980, led to little use in the market.

<span class="mw-page-title-main">MCS-51</span> Single chip microcontroller series by Intel

The Intel MCS-51 is a single chip microcontroller (MCU) series developed by Intel in 1980 for use in embedded systems. The architect of the Intel MCS-51 instruction set was John H. Wharton. Intel's original versions were popular in the 1980s and early 1990s, and enhanced binary compatible derivatives remain popular today. It is a complex instruction set computer, but also has some of the features of RISC architectures, such as a large register set and register windows, and has separate memory spaces for program instructions and data.

<span class="mw-page-title-main">Intel 8085</span> 8-bit microprocessor by Intel

The Intel 8085 ("eighty-eighty-five") is an 8-bit microprocessor produced by Intel and introduced in March 1976. It is the last 8-bit microprocessor developed by Intel.

<span class="mw-page-title-main">PIC microcontrollers</span> Line of single-chip microprocessors from Microchip Technology

PIC is a family of microcontrollers made by Microchip Technology, derived from the PIC1640 originally developed by General Instrument's Microelectronics Division. The name PIC initially referred to Peripheral Interface Controller, and is currently expanded as Programmable Intelligent Computer. The first parts of the family were available in 1976; by 2013 the company had shipped more than twelve billion individual parts, used in a wide variety of embedded systems.

x86 assembly language is the name for the family of assembly languages which provide some level of backward compatibility with CPUs back to the Intel 8008 microprocessor, which was launched in April 1972. It is used to produce object code for the x86 class of processors.

<span class="mw-page-title-main">Intel i960</span> RISC-based microprocessor design

Intel's i960 was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller. It became a best-selling CPU in that segment, along with the competing AMD 29000. In spite of its success, Intel stopped marketing the i960 in the late 1990s, as a result of a settlement with DEC whereby Intel received the rights to produce the StrongARM CPU. The processor continues to be used for a few military applications.

In computer science, computer engineering and programming language implementations, a stack machine is a computer processor or a virtual machine in which the primary interaction is moving short-lived temporary values to and from a push down stack. In the case of a hardware processor, a hardware stack is used. The use of a stack significantly reduces the required number of processor registers. Stack machines extend push-down automata with additional load/store operations or multiple stacks and hence are Turing-complete.

The TMS9900 was one of the first commercially available, single-chip 16-bit microprocessors. Introduced in June 1976, it implemented Texas Instruments' TI-990 minicomputer architecture in a single-chip format, and was initially used for low-end models of that lineup.

TLCS is a prefix applied to microcontrollers made by Toshiba. The product line includes multiple families of CISC and RISC architectures. Individual components generally have a part number beginning with "TMP". E.g. the TMP8048AP is a member of the TLCS-48 family.

The PDP-11 architecture is a 16-bit CISC instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). It is implemented by central processing units (CPUs) and microprocessors used in PDP-11 minicomputers. It was in wide use during the 1970s, but was eventually overshadowed by the more powerful VAX architecture in the 1980s.

<span class="mw-page-title-main">COP400</span> 4-bit microcontroller family

The COP400 or COP II is a 4-bit microcontroller family introduced in 1977 by National Semiconductor as a follow-on product to their original PMOS COP microcontroller. COP400 family members are complete microcomputers containing internal timing, logic, ROM, RAM, and I/O necessary to implement dedicated controllers. Some COP400 devices were second-sourced by Western Digital as the WD4200 family. In the Soviet Union several COP400 microcontrollers were manufactured as the 1820 series.

The MAC-8, better known today as the BELLMAC-8, is an 8-bit microprocessor designed by Bell Labs. Production began in CMOS form at Western Electric as the WE212 in 1977. The MAC-8 was used only in AT&T products, like the 4ESS. No commercial spec sheets were published, so it is little known as a result. The best-known use, in the public, is the MAC-TUTOR computer trainer, released in 1979.

References

  1. 1 2 3 4 Dr. Sung Mo (Steve) Kang (13 January 2015). "First-Hand:The AT&T BELLMAC-32 Microprocessor Development". Engineering and Technology History Wiki.
  2. ↑ "On The BELLMAC-32, And Perhaps The World's Largest Plotter Pen Drawing – greg.org". 2011-12-09. Retrieved 2024-03-28.
  3. ↑ "32-bit microprocessor IC news". Microsystems. June 1984. p. 12. Retrieved 25 March 2023.
  4. 1 2 3 4 5 Berenbaum, Alan D.; Condry, Michael W.; Lu, Priscilla M. (March 1982). "The Operating System and Language Support Features of the BELLMAC-32 Microprocessor". The Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems. Association for Computing Machinery: 30–38. Retrieved 24 March 2023.
  5. ↑ "WE 32100 Microprocessor Information Manual" (PDF). AT&T. January 1985.
  6. 1 2 "AT&T WE 32-Bit Microprocessors and Peripherals" (PDF). AT&T. August 1987.
  7. ↑ Huang, Victor K. L.; Seery, James W.; Wu, William S.; Altabet, Saul K.; Killian, Michael J.; Aymeloglu, Simeon; Gabara, Thaddeus J.; Fisher, Aaron L.; Hwang, Inseok S.; Thompson, David W. (April 1989). "The AT&T WE32200 Design Challenge". IEEE Micro. pp. 14–25. Retrieved 19 March 2023.
  8. ↑ Hunter, Bruce (June 1984). "AT&T Enters the Micro/Mini Market". Microsystems. pp. 114–116, 118. Retrieved 25 March 2023.
  9. ↑ "AT&T Offers 32-bit Processor to Other Companies". Byte. July 1985. p. 9. Retrieved 25 March 2023.
This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.