Domino logic

Last updated
General domino logic implementation, with the pull-down network symbolising a network of NMOS transistors. DominoLogic-LaTeX.png
General domino logic implementation, with the pull-down network symbolising a network of NMOS transistors.

Domino logic is a CMOS-based evolution of dynamic logic techniques consisting of a dynamic logic gate cascaded into a static CMOS inverter. [2] The term derives from the fact that in domino logic, each stage ripples the next stage for evaluation, similar to dominoes falling one after the other. Domino logic contrasts with other solutions to the cascade problem where cascading is interrupted by clocks or other means.

Contents

Domino logic was developed to speed up circuits, solving the premature cascade problem, typically by inserting static CMOS inverters between domino stages to avoid premature discharge of further cascaded dynamic logic gates. [3] Domino logic allows a rail-to-rail logic swing, with the output being able to switch from the power supply voltage to the ground voltage.

Dynamic logic

Dynamic logic differs from static logic by including a clock signal to speed up performance. In CMOS dynamic logic gates, the gate output is precharged to the power supply voltage while the clock is off (the "precharge" phase), and then is evaluated to the correct logic state while the clock is on (the "evaluation" phase) by draining the relevant NMOS transistors in the pull-down network. [2]

When cascading dynamic logic gates, however, a problem arises: the precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state. This uses up the precharge of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error. [4]

Domino logic operation

In order to cascade dynamic logic gates, one solution is domino logic, which inserts an ordinary static inverter between stages. In a multistage domino logic cascade structure, the evaluation of each stage ripples the next stage for evaluation, similar to dominoes falling one after the other. Once evaluated, the node states cannot return to "1" until the next precharge phase begins. [3]

While the insertion of the inverter might seem to defeat the point of dynamic logic, since the inverter has a pFET (one of the main goals of dynamic logic is to avoid pFETs where possible, due to speed), there are two reasons it works well. First, there is no fan-out to multiple pFETs; the dynamic gate connects to exactly one inverter, so the gate is still very fast. Furthermore, since the inverter connects to only nFETs in dynamic logic gates, it too is very fast. Second, the pFET in an inverter can be made smaller than in some types of logic gates. [5]

Modifications to domino logic

Charge sharing can cause difficulties for domino logic signal integrity; during the evaluation phase, NMOS transistors next to the output which are on may cause undesired discharging from the output node. To fix this, a keeper transistor can be used. This keeper transistor is a PMOS transistor with its gate connected to the inverter output, its source connected to the power supply, and its drain connected to the inverter input. The keeper transistor thus connects the dynamic node to the power supply whenever it is supposed to be in the "1" state, allowing the output to be correctly restored despite the charge sharing. [6]

Another issue in domino logic is its noninverting property; that is, it can only implement gates that do not have inversions at their outputs (such as AND gates and OR gates, as opposed to NAND gates and NOR gates). To rectify this property, some variants of domino logic are differential or dual-rail in nature, using inverted as well as non-inverted inputs to implement the logic function as well as its inverse. These varieties also include cross-coupled pFETs to attenuate noise. [2]

Traditional domino logic circuits are "footed", that is, they have an NMOS transistor controlled by the clock which is connected to the ground rail. Some domino logic circuits, however, are "footless": they lack this transistor, resulting in higher speed at the cost of greater power leakage. [7]

See also

Related Research Articles

<span class="mw-page-title-main">Logic gate</span> Device performing a Boolean function

A logic gate is a device that performs a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output. Depending on the context, the term may refer to an ideal logic gate, one that has, for instance, zero rise time and unlimited fan-out, or it may refer to a non-ideal physical device.

<span class="mw-page-title-main">Comparator</span> Device that compares two voltages or currents

In electronics, a comparator is a device that compares two voltages or currents and outputs a digital signal indicating which is larger. It has two analog input terminals and and one binary digital output . The output is ideally

N-type metal–oxide–semiconductor logic uses n-type (-) MOSFETs to implement logic gates and other digital circuits. These nMOS transistors operate by creating an inversion layer in a p-type transistor body. This inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs, nMOS transistors have four modes of operation: cut-off, triode, saturation, and velocity saturation.

<span class="mw-page-title-main">CMOS</span> Technology for constructing integrated circuits

Complementary metal–oxide–semiconductor is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.

<span class="mw-page-title-main">Static random-access memory</span> Type of computer memory

Static random-access memory is a type of random-access memory (RAM) that uses latching circuitry (flip-flop) to store each bit. SRAM is volatile memory; data is lost when power is removed.

<span class="mw-page-title-main">Inverter (logic gate)</span> Logic gate implementing negation

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. It outputs a bit opposite of the bit that is put into it. The bits are typically implemented as two differing voltage levels.

<span class="mw-page-title-main">Clock signal</span> Timing of electronic circuits

In electronics and especially synchronous digital circuits, a clock signal is an electronic logic signal which oscillates between a high and a low state at a constant frequency and is used like a metronome to synchronize actions of digital circuits. In a synchronous logic circuit, the most common type of digital circuit, the clock signal is applied to all storage devices, flip-flops and latches, and causes them all to change state simultaneously, preventing race conditions.

In computer engineering, a logic family is one of two related concepts:

<span class="mw-page-title-main">IC power-supply pin</span> Power supply connections for integrated circuits

IC power-supply pins denote a voltage and current supply terminals in electric, electronics engineering, and in Integrated circuit design. Integrated circuits (ICs) have at least two pins that connect to the power rails of the circuit in which they are installed. These are known as the power-supply pins. However, the labeling of the pins varies by IC family and manufacturer. The double subscript notation usually corresponds to a first letter in a given IC family (transistors) notation of the terminals.

<span class="mw-page-title-main">Depletion-load NMOS logic</span> Form of digital logic family in integrated circuits

In integrated circuits, depletion-load NMOS is a form of digital logic family that uses only a single power supply voltage, unlike earlier NMOS logic families that needed more than one different power supply voltage. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many microprocessors and other logic elements.

Power optimization is the use of electronic design automation tools to optimize (reduce) the power consumption of a digital design, such as that of an integrated circuit, while preserving the functionality.

<span class="mw-page-title-main">Integrated injection logic</span> Two-BJT transistor digital logic

Integrated injection logic (IIL, I2L, or I2L) is a class of digital circuits built with multiple collector bipolar junction transistors (BJT). When introduced it had speed comparable to TTL yet was almost as low power as CMOS, making it ideal for use in VLSI (and larger) integrated circuits. The gates can be made smaller with this logic family than with CMOS because complementary transistors are not needed. Although the logic voltage levels are very close (High: 0.7V, Low: 0.2V), I2L has high noise immunity because it operates by current instead of voltage. I2L was developed in 1971 by Siegfried K. Wiedmann and Horst H. Berger who originally called it merged-transistor logic (MTL). A disadvantage of this logic family is that the gates draw power when not switching unlike with CMOS.

In integrated circuit design, dynamic logic is a design methodology in combinational logic circuits, particularly those implemented in metal–oxide–semiconductor (MOS) technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high-speed digital electronics, particularly central processing units (CPUs). Dynamic logic circuits are usually faster than static counterparts and require less surface area, but are more difficult to design. Dynamic logic has a higher average rate of voltage transitions than static logic, but the capacitive loads being transitioned are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS or dynamic SOI design.

<span class="mw-page-title-main">Distributed amplifier</span>

Distributed amplifiers are circuit designs that incorporate transmission line theory into traditional amplifier design to obtain a larger gain-bandwidth product than is realizable by conventional circuits.

Four-phase logic is a type of, and design methodology for dynamic logic. It enabled non-specialist engineers to design quite complex ICs, using either PMOS or NMOS processes. It uses a kind of 4-phase clock signal.

<span class="mw-page-title-main">PMOS logic</span> Family of digital circuits

PMOS or pMOS logic is a family of digital circuits based on p-channel, enhancement mode metal–oxide–semiconductor field-effect transistors (MOSFETs). In the late 1960s and early 1970s, PMOS logic was the dominant semiconductor technology for large-scale integrated circuits before being superseded by NMOS and CMOS devices.

In electronics, pass transistor logic (PTL) describes several logic families used in the design of integrated circuits. It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Transistors are used as switches to pass logic levels between nodes of a circuit, instead of as switches connected directly to supply voltages. This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage. Each transistor in series is less saturated at its output than at its input. If several devices are chained in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional CMOS logic switches transistors so the output connects to one of the power supply rails, so logic voltage levels in a sequential chain do not decrease. Simulation of circuits may be required to ensure adequate performance.

<span class="mw-page-title-main">Depletion and enhancement modes</span> Two major types of field effect transistors

In field-effect transistors (FETs), depletion mode and enhancement mode are two major transistor types, corresponding to whether the transistor is in an on state or an off state at zero gate–source voltage.

<span class="mw-page-title-main">Memory cell (computing)</span> Part of computer memory

The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 and reset to store a logic 0. Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

References

  1. ↑ Sharma, Ankita; Rao, Divyanshu; Mohan, Ravi (December 2016). "Design and Implementation of Domino Logic Circuit in CMOS" (PDF). Journal of Network Communications and Emerging Technologies. 6 (12): 14–17.
  2. 1 2 3 Srivastava, P.; Pua, A.; Welch, L. (1998). "Issues in the design of domino logic circuits". Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222). IEEE Comput. Soc. pp. 108–112. doi:10.1109/GLSV.1998.665208. ISBN   978-0-8186-8409-8. S2CID   45670900.
  3. 1 2 Natarajan, Suriyaprakash; Gupta, Sandeep K.; Breuer, Melvin A. (2001). Proceedings International Test Conference 2001 (Cat. No.01CH37260). Vol. 13. IEEE. pp. 367–376. doi:10.1109/test.2001.966628. ISBN   0-7803-7169-0.
  4. ↑ Knepper, R.W. "5. Dynamic Logic Circuits". SC571 VLSI Design Principles. Boston University.
  5. ↑ WO 2000/076068,Abdel-Hafeez, S.&Ranjan, N.,"Single Rail Domino Logic For Four-Phase Clocking Scheme",published 2000
  6. ↑ Garg, Sandeep; Gupta, Tarun Kumar (2018-08-01). "Low power domino logic circuits in deep-submicron technology using CMOS". Engineering Science and Technology. 21 (4): 625–638. doi: 10.1016/j.jestch.2018.06.013 . ISSN   2215-0986.
  7. ↑ Angeline, A. Anita; Bhaaskaran, V. S. Kanchana (2022-04-01). "Domino Logic Keeper Circuit Design Techniques: A Review". Journal of the Institution of Engineers (India): Series B. 103 (2): 669–679. doi:10.1007/s40031-021-00668-5. ISSN   2250-2114. S2CID   256342548.

General references

This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.