Pass transistor logic

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In electronics, pass transistor logic (PTL) describes several logic families used in the design of integrated circuits. It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Transistors are used as switches to pass logic levels between nodes of a circuit, instead of as switches connected directly to supply voltages. [1] This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage (since pass transistors have some resistance and do not provide level restoration). Each transistor in series is less saturated at its output than at its input. [2] If several devices are chained in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional CMOS logic switches transistors so the output connects to one of the power supply rails (resembling an open collector scheme), so logic voltage levels in a sequential chain do not decrease. Simulation of circuits may be required to ensure adequate performance.

Contents

Applications

A six-transistor CMOS SRAM cell. M5 and M6 are bidirectional pass transistors. SRAM Cell (6 Transistors).svg
A six-transistor CMOS SRAM cell. M5 and M6 are bidirectional pass transistors.
a 10-transistor CMOS gated D latch, similar to the ones in the CD4042 or the CD74HC75 integrated circuits. Multiplexer-based latch using transmission gates.svg
a 10-transistor CMOS gated D latch, similar to the ones in the CD4042 or the CD74HC75 integrated circuits.

Pass transistor logic often uses fewer transistors, runs faster, and requires less power than the same function implemented with the same transistors in fully complementary CMOS logic. [3]

XOR has the worst-case Karnaugh map—if implemented from simple gates, it requires more transistors than any other function. Back when transistors were more expensive, designers of the Z80 and many other chips were motivated to save a few transistors by implementing the XOR using pass-transistor logic rather than simple gates. [4]

Basic principles of pass transistor circuits

MOSFET pass transistors are electronic switches that turn on or off the path between their drain and source depending on their gate's voltage signal (for instance the clock signal in the SRAM cell or gated D latch).

Because pass transistors do not provide level restoration and because their conducting path has a small non-zero resistance, there is increased RC delay for charging the next logic stage's input capacitance (which includes parasitic capacitance in addition to the next stage's gate capacitance) towards valid logic-high or logic-low voltage levels.

Simulation of circuits may be required to ensure adequate performance.

Complementary pass transistor logic

Some authors use the term "complementary pass transistor logic" to indicate a style of implementing logic gates that uses transmission gates composed of both NMOS and PMOS pass transistors. [5]

Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates where each gate consists of a NMOS-only pass transistor network, followed by a CMOS output inverter. [6] [7] [8]

Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates using dual-rail encoding. Every CPL gate has two output wires, both the positive signal and the complementary signal, eliminating the need for inverters. [9] [10] [11]

Complementary pass transistor logic or "Differential pass transistor logic" refers to a logic family which is designed for certain advantage. It is common to use this logic family for multiplexers and latches.[ citation needed ]

CPL uses series transistors to select between possible inverted output values of the logic, the output of which drives an inverter The CMOS transmission gates consist of nMOS and pMOS transistor connected in parallel.

Other forms

Static and dynamic types of pass transistor logic exist, with differing properties with respect to speed, power and low-voltage operation. [12] As integrated circuit supply voltages decrease, the disadvantages of pass transistor logic become more significant; the threshold voltage of transistors becomes large compared to the supply voltage, severely limiting the number of sequential stages. Because complementary inputs are often required to control pass transistors, additional logic stages are required.

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<span class="mw-page-title-main">MOSFET</span> Type of field-effect transistor

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NMOS or nMOS logic uses n-type (-) MOSFETs to implement logic gates and other digital circuits.

<span class="mw-page-title-main">CMOS</span> Technology for constructing integrated circuits

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<span class="mw-page-title-main">Inverter (logic gate)</span> Logic gate implementing negation

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<span class="mw-page-title-main">Emitter-coupled logic</span> Integrated circuit logic family

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<span class="mw-page-title-main">Depletion-load NMOS logic</span> Form of digital logic family in integrated circuits

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<span class="mw-page-title-main">Integrated injection logic</span> Two-BJT transistor digital logic

Integrated injection logic (IIL, I2L, or I2L) is a class of digital circuits built with multiple collector bipolar junction transistors (BJT). When introduced it had speed comparable to TTL yet was almost as low power as CMOS, making it ideal for use in VLSI (and larger) integrated circuits. The gates can be made smaller with this logic family than with CMOS because complementary transistors are not needed. Although the logic voltage levels are very close (High: 0.7V, Low: 0.2V), I2L has high noise immunity because it operates by current instead of voltage. I2L was developed in 1971 by Siegfried K. Wiedmann and Horst H. Berger who originally called it merged-transistor logic (MTL). A disadvantage of this logic family is that the gates draw power when not switching unlike with CMOS.

In integrated circuit design, dynamic logic is a design methodology in combinational logic circuits, particularly those implemented in metal–oxide–semiconductor (MOS) technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high-speed digital electronics, particularly central processing units (CPUs). Dynamic logic circuits are usually faster than static counterparts and require less surface area, but are more difficult to design. Dynamic logic has a higher average rate of voltage transitions than static logic, but the capacitive loads being transitioned are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS or dynamic SOI design.

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<span class="mw-page-title-main">Domino logic</span>

Domino logic is a CMOS-based evolution of dynamic logic techniques consisting of a dynamic logic gate cascaded into a static CMOS inverter. The term derives from the fact that in domino logic, each stage ripples the next stage for evaluation, similar to dominoes falling one after the other. Domino logic contrasts with other solutions to the cascade problem where cascading is interrupted by clocks or other means.

<span class="mw-page-title-main">PMOS logic</span> Family of digital circuits

PMOS or pMOS logic is a family of digital circuits based on p-channel, enhancement mode metal–oxide–semiconductor field-effect transistors (MOSFETs). In the late 1960s and early 1970s, PMOS logic was the dominant semiconductor technology for large-scale integrated circuits before being superseded by NMOS and CMOS devices.

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<span class="mw-page-title-main">Memory cell (computing)</span> Part of computer memory

The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 and reset to store a logic 0. Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

References

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Further reading