Pass transistor logic

Last updated June 09, 2024

In electronics, pass transistor logic (PTL) describes several logic families used in the design of integrated circuits. It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Transistors are used as switches to pass logic levels between nodes of a circuit, instead of as switches connected directly to supply voltages.^[1] This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage (since pass transistors have some resistance and do not provide level restoration). Each transistor in series is less saturated at its output than at its input.^[2] If several devices are chained in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional CMOS logic switches transistors so the output connects to one of the power supply rails (resembling an open collector scheme), so logic voltage levels in a sequential chain do not decrease. Simulation of circuits may be required to ensure adequate performance.

Applications

Pass transistor logic often uses fewer transistors, runs faster, and requires less power than the same function implemented with the same transistors in fully complementary CMOS logic.^[3]

XOR has the worst-case Karnaugh map—if implemented from simple gates, it requires more transistors than any other function. Back when transistors were more expensive, designers of the Z80 and many other chips were motivated to save a few transistors by implementing the XOR using pass-transistor logic rather than simple gates.^[4]

Basic principles of pass transistor circuits

MOSFET pass transistors are electronic switches that turn on or off the path between their drain and source depending on their gate's voltage signal (for instance the clock signal in the SRAM cell or gated D latch).

Because pass transistors do not provide level restoration and because their conducting path has a small non-zero resistance, there is increased RC delay for charging the next logic stage's input capacitance (which includes parasitic capacitance in addition to the next stage's gate capacitance) towards valid logic-high or logic-low voltage levels.

Simulation of circuits may be required to ensure adequate performance.

Complementary pass transistor logic

Some authors use the term "complementary pass transistor logic" to indicate a style of implementing logic gates that uses transmission gates composed of both NMOS and PMOS pass transistors.^[5]

Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates where each gate consists of a NMOS-only pass transistor network, followed by a CMOS output inverter.^[6]^[7]^[8]

Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates using dual-rail encoding. Every CPL gate has two output wires, both the positive signal and the complementary signal, eliminating the need for inverters.^[9]^[10]^[11]

Complementary pass transistor logic or "Differential pass transistor logic" refers to a logic family which is designed for certain advantage. It is common to use this logic family for multiplexers and latches.^{[ citation needed ]}

CPL uses series transistors to select between possible inverted output values of the logic, the output of which drives an inverter The CMOS transmission gates consist of nMOS and pMOS transistor connected in parallel.

Other forms

Static and dynamic types of pass transistor logic exist, with differing properties with respect to speed, power and low-voltage operation.^[12] As integrated circuit supply voltages decrease, the disadvantages of pass transistor logic become more significant; the threshold voltage of transistors becomes large compared to the supply voltage, severely limiting the number of sequential stages. Because complementary inputs are often required to control pass transistors, additional logic stages are required.

Related Research Articles

A logic gate is a device that performs a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output. Depending on the context, the term may refer to an ideal logic gate, one that has, for instance, zero rise time and unlimited fan-out, or it may refer to a non-ideal physical device.

<span class="mw-page-title-main">MOSFET</span> Type of field-effect transistor

In electronics, the metal–oxide–semiconductor field-effect transistor is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The term metal–insulator–semiconductor field-effect transistor (MISFET) is almost synonymous with MOSFET. Another near-synonym is insulated-gate field-effect transistor (IGFET).

NMOS or nMOS logic uses n-type (-) MOSFETs to implement logic gates and other digital circuits.

Complementary metal–oxide–semiconductor is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.

<span class="mw-page-title-main">Inverter (logic gate)</span> Logic gate implementing negation

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. It outputs a bit opposite of the bit that is put into it. The bits are typically implemented as two differing voltage levels.

<span class="mw-page-title-main">Emitter-coupled logic</span> Integrated circuit logic family

In electronics, emitter-coupled logic (ECL) is a high-speed integrated circuit bipolar transistor logic family. ECL uses an overdriven bipolar junction transistor (BJT) differential amplifier with single-ended input and limited emitter current to avoid the saturated region of operation and its slow turn-off behavior. As the current is steered between two legs of an emitter-coupled pair, ECL is sometimes called current-steering logic (CSL), current-mode logic (CML) or current-switch emitter-follower (CSEF) logic.

The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function and sizing gates to achieve the minimum delay possible for a circuit.

Resistor–transistor logic (RTL), sometimes also known as transistor–resistor logic (TRL), is a class of digital circuits built using resistors as the input network and bipolar junction transistors (BJTs) as switching devices. RTL is the earliest class of transistorized digital logic circuit; it was succeeded by diode–transistor logic (DTL) and transistor–transistor logic (TTL).

In computer engineering, a logic family is one of two related concepts:

In integrated circuits, depletion-load NMOS is a form of digital logic family that uses only a single power supply voltage, unlike earlier NMOS logic families that needed more than one different power supply voltage. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many microprocessors and other logic elements.

XOR gate is a digital logic gate that gives a true output when the number of true inputs is odd. An XOR gate implements an exclusive or from mathematical logic; that is, a true output results if one, and only one, of the inputs to the gate is true. If both inputs are false (0/LOW) or both are true, a false output results. XOR represents the inequality function, i.e., the output is true if the inputs are not alike otherwise the output is false. A way to remember XOR is "must have one or the other but not both".

Power optimization is the use of electronic design automation tools to optimize (reduce) the power consumption of a digital design, such as that of an integrated circuit, while preserving the functionality.

Diode logic constructs AND and OR logic gates with diodes and resistors.

Integrated injection logic (IIL, I²L, or I2L) is a class of digital circuits built with multiple collector bipolar junction transistors (BJT). When introduced it had speed comparable to TTL yet was almost as low power as CMOS, making it ideal for use in VLSI (and larger) integrated circuits. The gates can be made smaller with this logic family than with CMOS because complementary transistors are not needed. Although the logic voltage levels are very close (High: 0.7V, Low: 0.2V), I2L has high noise immunity because it operates by current instead of voltage. I2L was developed in 1971 by Siegfried K. Wiedmann and Horst H. Berger who originally called it merged-transistor logic (MTL). A disadvantage of this logic family is that the gates draw power when not switching unlike with CMOS.

In integrated circuit design, dynamic logic is a design methodology in combinational logic circuits, particularly those implemented in metal–oxide–semiconductor (MOS) technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high-speed digital electronics, particularly central processing units (CPUs). Dynamic logic circuits are usually faster than static counterparts and require less surface area, but are more difficult to design. Dynamic logic has a higher average rate of voltage transitions than static logic, but the capacitive loads being transitioned are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS or dynamic SOI design.

Multi-threshold CMOS (MTCMOS) is a variation of CMOS chip technology which has transistors with multiple threshold voltages (V_th) in order to optimize delay or power. The V_th of a MOSFET is the gate voltage where an inversion layer forms at the interface between the insulating layer (oxide) and the substrate (body) of the transistor. Low V_th devices switch faster, and are therefore useful on critical delay paths to minimize clock periods. The penalty is that low V_th devices have substantially higher static leakage power. High V_th devices are used on non-critical paths to reduce static leakage power without incurring a delay penalty. Typical high V_th devices reduce static leakage by 10 times compared with low V_th devices.

$<span class="mw-page-title-main">Domino logic</span>$

Domino logic is a CMOS-based evolution of dynamic logic techniques consisting of a dynamic logic gate cascaded into a static CMOS inverter. The term derives from the fact that in domino logic, each stage ripples the next stage for evaluation, similar to dominoes falling one after the other. Domino logic contrasts with other solutions to the cascade problem where cascading is interrupted by clocks or other means.

<span class="mw-page-title-main">PMOS logic</span> Family of digital circuits

PMOS or pMOS logic is a family of digital circuits based on p-channel, enhancement mode metal–oxide–semiconductor field-effect transistors (MOSFETs). In the late 1960s and early 1970s, PMOS logic was the dominant semiconductor technology for large-scale integrated circuits before being superseded by NMOS and CMOS devices.

Power gating is a technique used in integrated circuit design to reduce power consumption, by shutting off the current to blocks of the circuit that are not in use. In addition to reducing stand-by or leakage power, power gating has the benefit of enabling Iddq testing.

<span class="mw-page-title-main">Memory cell (computing)</span> Part of computer memory

The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 and reset to store a logic 0. Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

References

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↑ Maxfield, Clive (2008). Bebop to the boolean boogie: an unconventional guide to electronics. Newnes. pp. 423–6. ISBN 978-1-85617-507-4.
↑ Norimitsu Sako. "Patent US7171636: Pass-transistor logic circuit and a method of designing thereof". 'It is known in the art to employ a "pass-transistor logic circuit" to reduce a number of elements and power consumption, and to improve operating speed.'
↑ Shirriff, Ken (2013). "Reverse-engineering the Z-80: the silicon for two interesting gates explained".
↑ Yeap, Gary K. (2012) [1998]. Practical Low Power Digital VLSI Design. Springer. p. 197. ISBN 978-1-4615-6065-4.
↑ Oklobdzija, Vojin G. (19 December 2017). Digital Design and Fabrication. CRC Press. pp. 2–39. ISBN 9780849386046.
↑ Yano, Kuniaki; Yamanaka, Toshiaki Yamanaka; Nishida, Takeshi; Saito, Mitsuo; Shimohigashi, Katsuhiro; Shimizu, Atsushi (1990). "A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic". IEEE Journal of Solid-State Circuits . 25 (2): 388–395. Bibcode:1990IJSSC..25..388Y. doi:10.1109/4.52161.
↑ Reynders, Nele; Dehaene, Wim (2015). Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits. Analog Circuits And Signal Processing (ACSP). Springer Switzerland. doi:10.1007/978-3-319-16136-5. ISBN 978-3-319-16135-8. ISSN 1872-082X. LCCN 2015935431.
↑ Chen, Wai-Kai, ed. (2003). Logic Design. CRC Press. pp. 15–7. ISBN 978-0-203-01015-0. OCLC 1029500642.
↑ Oklobdzija, Vojin G., ed. (2001). The Computer Engineering Handbook. Taylor & Francis. pp. 2-23–2-24. ISBN 978-0-8493-0885-7.
↑ Pal, Ajit (2014). "5.2.3 Pass-Transistor Logic Families". Low-Power VLSI Circuits and Systems. Springer. pp. 109–110. ISBN 978-81-322-1937-8.
↑ Leondes, Cornelius T. (1995). Digital signal processing systems: implementation techniques. Elsevier. p. 2. ISBN 0-12-012768-7.

v t e Logic families
MOS technology	PMOS logic NMOS logic Depletion-load NMOS logic (including HMOS) Complementary MOS (CMOS) Pass transistor logic (PTL) Bipolar–CMOS (BiCMOS)
Other technologies	Diode logic Diode–transistor logic (DTL) Open collector (OC) Direct-coupled transistor logic (DCTL) Emitter-coupled logic (ECL) Gunning transceiver logic (GTL) Integrated injection logic (I²L) Resistor–transistor logic (RTL) Transistor–transistor logic (TTL) Current mode logic / Source-coupled logic (CML/SCL)
Types	Static Dynamic Domino logic Four-phase logic