Dana Fisman | |
---|---|
Alma mater | Technion – Israel Institute of Technology, Weizmann Institute of Science |
Known for | Reconstruction of automaton-based models, temporal logic, Property Specification Language, program synthesis |
Scientific career | |
Fields | Computer Science |
Institutions | Ben-Gurion University of the Negev |
Thesis | (2006) |
Doctoral advisor | Amir Pnueli |
Dana Fisman is an Israeli computer scientist whose research has included work on the reconstruction of automaton-based models in computational learning theory including induction of regular languages, on temporal logic and the Property Specification Language, and on program synthesis. She is an associate professor of computer science at Ben-Gurion University of the Negev. [1]
Fisman earned a bachelor's degree from the Technion – Israel Institute of Technology in 1997. [2] She went to the Weizmann Institute of Science for graduate study in computer science, earning both a master's degree and a Ph.D. there. [1] She completed her doctorate in 2006, under the supervision of Amir Pnueli. [3]
After her doctoral work, she became a postdoctoral researcher at the Hebrew University of Jerusalem. [1] Meanwhile, she had been working in industry at the IBM Haifa Research Lab from 1997 to 2009; [2] there she became one of the developers of the Property Specification Language for temporal logic. [4] She moved to Synopsys, from 2009 to 2013. [2]
In 2013 she returned to academia. She became a visiting fellow at Yale University from 2013 to 2016, and a research scientist at the University of Pennsylvania from 2014 to 2016. [2] At the University of Pennsylvania she was associate director of a project on program synthesis headed by Rajeev Alur. [4] [5] In 2016 she obtained a position as assistant professor of computer science at Ben-Gurion University, and in 2021 she was promoted to associate professor. [2]
Fisman is coauthor, with Cindy Eisner, of the book A Practical Introduction to PSL (Springer, 2006). [6]
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In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of a system with respect to a certain formal specification or property, using formal methods of mathematics. Formal verification is a key incentive for formal specification of systems, and is at the core of formal methods. It represents an important dimension of analysis and verification in electronic design automation and is one approach to software verification. The use of formal verification enables the highest Evaluation Assurance Level (EAL7) in the framework of common criteria for computer security certification.
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Property Specification Language (PSL) is a temporal logic extending linear temporal logic with a range of operators for both ease of expression and enhancement of expressive power. PSL makes an extensive use of regular expressions and syntactic sugaring. It is widely used in the hardware design and verification industry, where formal verification tools and/or logic simulation tools are used to prove or refute that a given PSL formula holds on a given design.
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