Eby Friedman

Last updated
Eby G. Friedman
Eby-G.-Friedman.jpg
Friedman in 2008
Born (1957-08-10) 10 August 1957 (age 66)
Jersey City, New Jersey
Education Lafayette College
University of California, Irvine
Awards IEEE Fellow
IEEE CAS Charles A. Desoer Technical Achievement Award
Fulbright Scholar
University of California, Irvine Engineering Hall of Fame
IEEE CAS Mac Van Valkenburg Award
Scientific career
Fields Electrical and Computer Engineering
Institutions University of Rochester
Technion – Israel Institute of Technology
Hughes Aircraft Company
Doctoral advisor James H. Mulligan, Jr.
Website www.ece.rochester.edu/~friedman

Eby G. Friedman is an electrical engineer, and Distinguished Professor of Electrical and Computer Engineering at the University of Rochester. Friedman is also a visiting professor at the Technion - Israel Institute of Technology. He is a Senior Fulbright Fellow and a Fellow of the IEEE.

Contents

Early life and education

Born in Jersey City, New Jersey, in 1957, [1] [2] he earned an electrical engineering baccalaureate degree from Lafayette College in 1979, a master's degree (1981) and a doctoral degree (1989) from the University of California, Irvine, also in electrical engineering. [3] Friedman graduated from Snyder High School in Jersey City, New Jersey in 1975. Friedman married his wife Laurie in 1984, and they have two sons. [4]

Career

Friedman's research interests include integrated circuits, VLSI design and analysis, clock synchronization, power delivery, 3-D integration, superconductive single flux quantum circuits, and mixed-signal circuits. [5]

His career began in the Netherlands in 1978, working at Philips Gloeilampen Fabreiken on designing bipolar differential amplifiers. [1] From 1979 to 1991 he worked at Hughes Aircraft Company, developing a large variety of integrated circuits for US military and commercial applications. [6] He joined the Electrical and Computer Engineering faculty at the University of Rochester in 1991. [6]

Friedman became a Fellow of the IEEE in 2000 and a Fulbright Scholar (at the Technion in Israel) in 2001. He received the 2005 William H. Riker University Award for Graduate Teaching at the University of Rochester. [7] In 2012 he became a Distinguished Lecturer of the IEEE CAS Society,[ citation needed ] and in 2013, he was awarded the Charles A. Desoer Technical Achievement Award,. [8] In October 2015 he was inducted into the University of California, Irvine, Engineering Hall of Fame. [9] He received the IEEE CAS Mac Van Valkenburg award in 2018. [10] He received the University of Rochester Hajim Lifetime Achievement Award in 2024.

Service

Editing

Friedman is a member of the editorial board of the Journal of Low Power Electronics and Applications. [11] He is a past editor-in-chief and chair of the steering committee for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, [12] past editor-in-chief of the Microelectronics Journal, as well as past regional editor of the Journal of Circuits, Systems and Computers. [13] He formerly served as a member of several editorial boards: Analog Integrated Circuits and Signal Processing, [13] Journal of VLSI Signal Processing,[ citation needed ], Proceedings of the IEEE and IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing.[ citation needed ]

Committee work

Friedman has served multiple IEEE societies and committees: Circuits and Systems (CAS) Society Board of Governors and CAS liaison to the Solid-State Circuits Society (SSCS);[ citation needed ] past chair of the VLSI Systems and Applications Circuits and Systems Society Technical Committee; [14] and past chair of the Electron Devices Chapter of the Rochester Section.[ citation needed ]

Selected workshops and conferences

He was General/Program/Technical Co-Chair, for the 1997 International Workshop on Clock Distribution Networks. [15] He has also chaired the following IEEE events: the 2000 Workshop on Signal Processing Systems, [16] the 2003 and 2004 IEEE International Workshop on System-on-Chip for Real-Time Applications, [17] technical program chair of the 2004 IEEE International Conference on Electronics, Circuits, and Systems, [18] the 2006 IEEE International Symposium on Circuits and Systems, [19] and the 2007 IEEE International Symposium on Networks on Chip (NoC). [20]

Publications and patents

Friedman has published almost 600 papers [21] and is co-inventor of 29 patents. [22]

Books

Selected articles

Related Research Articles

<span class="mw-page-title-main">Integrated circuit</span> Electronic circuit formed on a small, flat piece of semiconductor material

An integrated circuit (IC), also known as a microchip, computer chip, or simply chip, is a small electronic device made up of multiple interconnected electronic components such as transistors, resistors, and capacitors. These components are etched onto a small piece of semiconductor material, usually silicon. Integrated circuits are used in a wide range of electronic devices, including computers, smartphones, and televisions, to perform various functions such as processing and storing information. They have greatly impacted the field of electronics by enabling device miniaturization and enhanced functionality.

<span class="mw-page-title-main">CMOS</span> Technology for constructing integrated circuits

Complementary metal–oxide–semiconductor is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.

<span class="mw-page-title-main">Clock signal</span> Timing of electronic circuits

In electronics and especially synchronous digital circuits, a clock signal is an electronic logic signal which oscillates between a high and a low state at a constant frequency and is used like a metronome to synchronize actions of digital circuits. In a synchronous logic circuit, the most common type of digital circuit, the clock signal is applied to all storage devices, flip-flops and latches, and causes them all to change state simultaneously, preventing race conditions.

Neuromorphic computing is an approach to computing that is inspired by the structure and function of the human brain. A neuromorphic computer/chip is any device that uses physical artificial neurons to do computations. In recent times, the term neuromorphic has been used to describe analog, digital, mixed-mode analog/digital VLSI, and software systems that implement models of neural systems. The implementation of neuromorphic computing on the hardware level can be realized by oxide-based memristors, spintronic memories, threshold switches, transistors, among others. Training software-based neuromorphic systems of spiking neural networks can be achieved using error backpropagation, e.g., using Python based frameworks such as snnTorch, or using canonical learning rules from the biological learning literature, e.g., using BindsNet.

<span class="mw-page-title-main">Carver Mead</span> American scientist and engineer

Carver Andress Mead is an American scientist and engineer. He currently holds the position of Gordon and Betty Moore Professor Emeritus of Engineering and Applied Science at the California Institute of Technology (Caltech), having taught there for over 40 years.

<span class="mw-page-title-main">Mixed-signal integrated circuit</span> Integrated circuit

A mixed-signal integrated circuit is any integrated circuit that has both analog circuits and digital circuits on a single semiconductor die. Their usage has grown dramatically with the increased use of cell phones, telecommunications, portable electronics, and automobiles with electronics and digital sensors.

Clock skew is a phenomenon in synchronous digital circuit systems in which the same sourced clock signal arrives at different components at different times due to gate or, in more advanced semiconductor technology, wire signal propagation delay. The instantaneous difference between the readings of any two clocks is called their skew.

Rent's rule pertains to the organization of computing logic, specifically the relationship between the number of external signal connections to a logic block with the number of logic gates in the logic block, and has been applied to circuits ranging from small digital circuits to mainframe computers. Put simply, it states that there is a simple power law relationship between these two values.

A field-programmable analog array (FPAA) is an integrated circuit device containing computational analog blocks (CAB) and interconnects between these blocks offering field-programmability. Unlike their digital cousin, the FPGA, the devices tend to be more application driven than general purpose as they may be current mode or voltage mode devices. For voltage mode devices, each block usually contains an operational amplifier in combination with programmable configuration of passive components. The blocks can, for example, act as summers or integrators.

<span class="mw-page-title-main">Multi-project wafer service</span>

Multi-project chip (MPC), and multi-project wafer (MPW) semiconductor manufacturing arrangements allow customers to share tooling and microelectronics wafer fabrication cost between several designs or projects.

Giovanni De Micheli is a research scientist in electronics and computer science. He is credited for the invention of the Network on a Chip design automation paradigm and for the creation of algorithms and design tools for Electronic Design Automation (EDA). He is Professor and Director of the Integrated Systems laboratory at École Polytechnique Fédérale de Lausanne (EPFL), Switzerland. Previously, he was Professor of Electrical Engineering at Stanford University. He was Director of the Electrical Engineering Institute at EPFL from 2008 to 2019 and program leader of the Swiss Federal Nano-Tera.ch program. He holds a Nuclear Engineer degree, a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science under Alberto Sangiovanni-Vincentelli.

<span class="mw-page-title-main">Leon O. Chua</span> American electrical engineer and computer scientist

Leon Ong Chua is an American electrical engineer and computer scientist. He is a professor in the electrical engineering and computer sciences department at the University of California, Berkeley, which he joined in 1971. He has contributed to nonlinear circuit theory and cellular neural network theory.

A physical neural network is a type of artificial neural network in which an electrically adjustable material is used to emulate the function of a neural synapse or a higher-order (dendritic) neuron model. "Physical" neural network is used to emphasize the reliance on physical hardware used to emulate neurons as opposed to software-based approaches. More generally the term is applicable to other artificial neural networks in which a memristor or other electrically adjustable resistance material is used to emulate a neural synapse.

<span class="mw-page-title-main">Ian A. Young</span> American electrical engineer

Ian A. Young is an Intel engineer. Young is a co-author of 50 research papers, and has 71 patents in switched capacitor circuits, DRAM, SRAM, BiCMOS, x86 clocking, Photonics and spintronics.

Rajiv V. Joshi is an Indian-American prolific inventor and research staff member at IBM's Thomas J. Watson Research Center. His work focuses on the development of integrated circuits and memory chips. He is an IEEE Fellow and received the Industrial Pioneer Award from the IEEE Circuits and Systems Society in 2013 and the IEEE Daniel E. Noble Award in 2018. He holds 271 U.S. patents.

Kenneth L Shepard is an American electrical engineer, nanoscientist, entrepreneur, and the Lau Family Professor of Electrical Engineering and Biomedical Engineering at the Columbia School of Engineering and Applied Science (Columbia). Shepard was born in Bryn Mawr, Pennsylvania.

<span class="mw-page-title-main">Nader Bagherzadeh</span> American academic

Nader Bagherzadeh is a professor of computer engineering in the Department of Electrical Engineering and Computer Science at the University of California, Irvine, where he served as a chair from 1998 to 2003. Bagherzadeh has been involved in research and development in the areas of: Computer Architecture, Reconfigurable Computing, VLSI Chip Design, Network-on-Chip, 3D chips, Sensor Networks, Computer Graphics, Memory and Embedded Systems. Bagherzadeh was named Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2014 for contributions to the design and analysis of coarse-grained reconfigurable processor architectures. Bagherzadeh has published more than 400 articles in peer-reviewed journals and conferences. He was with AT&T Bell Labs from 1980 to 1984.

RF CMOS is a metal–oxide–semiconductor (MOS) integrated circuit (IC) technology that integrates radio-frequency (RF), analog and digital electronics on a mixed-signal CMOS RF circuit chip. It is widely used in modern wireless telecommunications, such as cellular networks, Bluetooth, Wi-Fi, GPS receivers, broadcasting, vehicular communication systems, and the radio transceivers in all modern mobile phones and wireless networking devices. RF CMOS technology was pioneered by Pakistani engineer Asad Ali Abidi at UCLA during the late 1980s to early 1990s, and helped bring about the wireless revolution with the introduction of digital signal processing in wireless communications. The development and design of RF CMOS devices was enabled by van der Ziel's FET RF noise model, which was published in the early 1960s and remained largely forgotten until the 1990s.

<span class="mw-page-title-main">Mohamad Sawan</span> Canadian engineer

Mohamad Sawan is a Canadian-Lebanese electrical engineer, academic and researcher. He is a Chair Professor at Westlake University, China, and an Emeritus Professor of Electrical Engineering at Polytechnique Montréal, Canada.

References

  1. 1 2 "Eby G. Friedman's Homepage". www2.ece.rochester.edu. Retrieved 2017-12-13.
  2. ↑ Deckert, Andrea. "Researcher, teacher are among the many hats he wears", Rochester Business Journal, April 4, 2008. Accessed March 22, 2023. "He may be a giant in the world of microchip design, but Eby Friedman sees himself as more of a kid from Jersey City.... Friedman was born and raised in Jersey City, N.J. He could see the Statue of Liberty from his high school chemistry class."
  3. ↑ "Manhattan Routing Welcomes Eby Friedman, IEEE Fellow and Distinguished Professor at the University of Rochester, to Technical Advisory Board". www.businesswire.com. 2004-06-07. Retrieved 2017-12-13.
  4. ↑ "Connecticut Marriage Index, 1959-2012" . Ancestry.com. 10 June 1984. Retrieved 2017-12-13.
  5. ↑ "Directory: Electrical and Computer Engineering". Ece.rochester.edu. Retrieved 2015-12-17.
  6. 1 2 Friedman, Eby (2009). "Design Challenges in High Performance Three-Dimensional Circuits". Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09. pp. 281–282. doi:10.1145/1531542.1531545. ISBN   9781605585222. S2CID   1463358.
  7. ↑ "William H. Riker University Award for Excellence in Graduate Teaching". www.rochester.edu. Office of the Provost, University of Rochester. Retrieved 2017-12-13.
  8. ↑ "Charles A. Desoer Technical Achievement Award | IEEE Circuits and Systems Society". Ieee-cas.org. Archived from the original on 2016-02-23. Retrieved 2015-07-14.
  9. ↑ "2015 Hall of Fame Inductees | The Henry Samueli School of Engineering at UC Irvine". engineering.uci.edu. Retrieved 2017-12-13.
  10. ↑ "IEEE Circuits and Systems Society Mac Van Valkenburg Award". ieee-cas.org. Retrieved 2018-05-18.
  11. ↑ "Editors of JLPEA". MDPI. Retrieved 2017-05-08.
  12. ↑ "Past Editors in Chief - IEEE CAS". ieee-cas.org. Retrieved 2017-12-13.
  13. 1 2 "Power Delivery in Heterogeneous Nanoscale Integrated Circuits | EE". www.ee.ucla.edu. August 2017. Retrieved 2017-12-13.
  14. ↑ "Officers and Members". ieee-cas.org. Retrieved 2015-07-14.
  15. ↑ "Publications search" (PDF). springer.com. Retrieved 2015-07-14.[ dead link ]
  16. ↑ "2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528)". 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. IEEE. October 2000. pp. i–. doi:10.1109/SIPS.2000.886697. ISBN   978-0-7803-6488-2.
  17. ↑ "4th IEEE International Workshop on System-on-Chip for Real-Time Applications". IEEE. 2004. Retrieved 2015-07-14.
  18. ↑ "ICECS 2004 11th IEEE International Conference on Electronics, Circuits and Systems - Call for Participation". IEEE Circuits and Devices Magazine. 20 (2): 47. 2004. doi:10.1109/MCD.2004.1276210.
  19. ↑ "Publications search" (PDF). ieee-cas.org. Archived from the original (PDF) on 2016-03-30. Retrieved 2015-07-14.
  20. ↑ "Message from the General and Program Chairs". First International Symposium on Networks-on-Chip (NOCS'07). IEEE. 2007. pp. ix. doi:10.1109/NOCS.2007.28. ISBN   978-0-7695-2773-4.{{cite book}}: |website= ignored (help)
  21. ↑ "Eby G. Friedman/Publications" . Retrieved 2014-07-14.
  22. ↑ "Eby G. Friedman/Patents". www2.ece.rochester.edu. Retrieved 2017-12-13.
  23. ↑ Eby G. Friedman (1995). Clock distribution networks in VLSI circuits and systems. Institute of Electrical and Electronics Engineers. ISBN   978-0-7803-1058-2.
  24. ↑ Eby G. Friedman (6 December 2012). High Performance Clock Distribution Networks. Springer Science & Business Media. ISBN   978-1-4684-8440-3.
  25. 1 2 Juan J. Becerra; Eby G. Friedman (6 December 2012). Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997). Springer Science & Business Media. ISBN   978-1-4615-6101-9.
  26. ↑ "On-Chip Inductance in High-Speed Integrated Circuits" (PDF). Ece.northwestern.edu. Archived from the original (PDF) on 2015-06-15. Retrieved 2014-07-14.
  27. ↑ Mezhiba, Andrey V.; Friedman, Eby G. (2004). Power Distribution Networks in High Speed Integrated Circuits. Springer. doi:10.1007/978-1-4615-0399-6. ISBN   9781402075346.
  28. ↑ Kursun, Volkan; Friedman, Eby G. (2006). Multi-Voltage CMOS Circuit Design. doi:10.1002/0470033371. ISBN   9780470033371.
  29. ↑ Mikhail Popovich; Andrey V. Mezhiba; Selçuk Köse; Eby Friedman (2010-11-23). Power Distribution Networks with On-Chip Decoupling Capacitors (PDF). Ihome.ust.hk. ISBN   9781441978714 . Retrieved 2014-07-14.
  30. ↑ F. Pavlidis; Eby G. Friedman. "Three-Dimensional Integrated Circuit Design". Elsevier Inc. Retrieved 2014-07-14.
  31. ↑ Emre Salman; Eby Friedman (2012-08-14). High Performance Integrated Circuit Design. McGraw Hill Professional. ISBN   9780071635752 . Retrieved 2014-07-14.
  32. ↑ Vaisband, Inna; Price, Burt; Köse, Selçuk; Kolla, Yesh; Friedman, Eby G.; Fischer, Jeff (2015-06-01). "Distributed LDO regulators in a 28 nm power delivery system". Analog Integrated Circuits and Signal Processing. 83 (3): 295–309. CiteSeerX   10.1.1.696.126 . doi:10.1007/s10470-015-0526-y. ISSN   0925-1030. S2CID   18083154.
  33. ↑ Vaisband, Inna; Friedman, Eby G. (2015). "Energy efficient adaptive clustering of on-chip power delivery systems". INTEGRATION, the VLSI Journal. 48: 1–9. doi:10.1016/j.vlsi.2014.06.003. S2CID   15215718.
  34. ↑ Kazemi, M.; Ipek, E.; Friedman, E. G. (November 2014). "Adaptive Compact Magnetic Tunnel Junction Model". IEEE Transactions on Electron Devices. 61 (11): 3883–3891. Bibcode:2014ITED...61.3883K. CiteSeerX   10.1.1.696.1705 . doi:10.1109/TED.2014.2359627. ISSN   0018-9383. S2CID   14660614.
  35. ↑ Kvatinsky, S.; Satat, G.; Wald, N.; Friedman, E. G.; Kolodny, A.; Weiser, U. C. (October 2014). "Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22 (10): 2054–2066. CiteSeerX   10.1.1.696.2360 . doi:10.1109/TVLSI.2013.2282132. ISSN   1063-8210. S2CID   166787.
  36. ↑ Shapiro, Alexander; Friedman, Eby G. (2014-06-11). "MOS Current Mode Logic Near Threshold Circuits". Journal of Low Power Electronics and Applications. 4 (2): 138–152. doi: 10.3390/jlpea4020138 .
  37. ↑ Patel, Ravi; Ipek, Engin; Friedman, Eby G. (2014-02-01). "2T–1R STT-MRAM memory cells for enhanced on/off current ratio". Microelectronics Journal. 45 (2): 133–143. doi:10.1016/j.mejo.2013.11.015. ISSN   0026-2692.
  38. ↑ Kvatinsky, S.; Nacson, Y. H.; Etsion, Y.; Friedman, E. G.; Kolodny, A.; Weiser, U. C. (January 2014). "Memristor-Based Multithreading". IEEE Computer Architecture Letters. 13 (1): 41–44. CiteSeerX   10.1.1.386.4974 . doi:10.1109/L-CA.2013.3. ISSN   1556-6056. S2CID   9770099.
  39. ↑ Eby G. Friedman. "Clock Distribution Networks in Synchronous Digital Integrated Circuits" (PDF). Eecs.wsu.edu. Archived from the original (PDF) on 2015-06-01. Retrieved 2014-07-14.
  40. ↑ Ismail, Y. I.; Friedman, E. G. (April 2000). "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8 (2): 195–206. CiteSeerX   10.1.1.134.9284 . doi:10.1109/92.831439. ISSN   1063-8210.
  41. ↑ Ismail, Y. I.; Friedman, E. G.; Neves, J. L. (June 1998). "Figures of merit to characterize the importance of on-chip inductance". Proceedings of the 35th annual conference on Design automation conference - DAC '98. pp. 560–565. CiteSeerX   10.1.1.32.2950 . doi:10.1145/277044.277193. ISBN   978-0897919647. S2CID   5478003.
  42. ↑ Haurylau, M.; Chen, G.; Chen, H.; Zhang, J.; Nelson, N. A.; Albonesi, D. H.; Friedman, E. G.; Fauchet, P. M. (November 2006). "On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions". IEEE Journal of Selected Topics in Quantum Electronics. 12 (6): 1699–1705. Bibcode:2006IJSTQ..12.1699H. doi:10.1109/JSTQE.2006.880615. ISSN   1077-260X. S2CID   2720738.
This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.