IMP-16

National Semiconductor IMP-16

IMP-16A, one of four RALU chips
General information
Launched	1973;53 years ago (1973)
Common manufacturer	National Semiconductor
Performance
Max. CPU clock rate	to 715 KHz
Data width	16
Address width	16
Architecture and classification
Number of instructions	43
Physical specifications
Package	five or six 24-pin DIPs
History
Successor	PACE

The IMP-16, by National Semiconductor, was the first multi-chip 16-bit microprocessor, released in 1973. It consisted of five PMOS integrated circuits: four identical RALU chips, short for register and ALU, providing the data path, and one CROM, Control and ROM, providing control sequencing and microcode storage. The IMP-16 is a bit-slice processor; each RALU chip provides a 4-bit slice of the register and arithmetic that work in parallel to produce a 16-bit word length. ^{[1] [2]}

Configuration

Each RALU chip stores its own 4 bits of the program counter, several registers, the ALU, a 16-word LIFO stack, and status flags. There are four 16-bit accumulators, two of which could be used as index registers. The instruction set architecture was similar to that of the Data General Nova. Like the Nova, the smallest unit of addressable and writable memory is the 16-bit word; byte-level writes are not supported. IMP-16 can address up to 64K words (128K bytes). The chip set can be extended with the CROM II chip (IMP-16A / 522D) that implements 16-bit multiply and divide routines plus byte operations. Byte support is limited to the lower 32K words of memory. ^[3] The chipset is driven by a 715 kHz four-phase non-overlapping clock with a +5 to -12 voltage swing. An integral part of the architecture is a 16-bit input mux that provided various condition bits from the ALUs such as zero, carry, overflow along with general purpose inputs.

Applications

The microprocessor was used in the IMP-16P microcomputer and Jacquard Systems' J100 but saw little other use. ^{[4] [5]} The IMP-16 was later superseded by the PACE and INS8900 single-chip 16-bit microprocessors, which had a similar architecture but were not binary compatible. It was also used in the Aston Martin Lagonda, thanks to National Semiconductor's chairman Peter Sprague being a major shareholder in Aston Martin at the time. ^[6]

Example code

The following assembler source code is for a subroutine CPYMEM that copies words from one location to another. All instructions in basic instruction set are one word.

1000 1000 8200 1001 A300 1002 4A01 1003 4B01 1004 49FF 1005 22FA 1006 0200

; Copy memory words addressed by AC2 to location addressed; by AC3 for a number of words contained in AC1.; AC0 through AC3 equated to 0 through 3.=X*1000CPYMEM:LDAC0,0(AC2); Get word to copy @AC2STAC0,0(AC3); Save word @AC3AISZAC2,1; Bump source pointerAISZAC3,1; Bump dest pointerAISZAC1,-1; Decrement word count, skip if 0JMPCPYMEM; else loop for all wordsRTS0; Return

IMP-16 registers

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) Main registers AC0 Accumulator AC1 Accumulator AC2 Acc/Base AC3 Acc/Base Program counter PC Program Counter Stack STK (16 entries) Status Flags Register (FR) L OV CY GF GF GF GF GF GF GF GF GF GF GF GF GF Status

References

1. "Use of RALU flags" ^{[ permanent dead link ]}.
2. "IMP-00A/520 MOS/LSI register and arithmetic logic unit (RALU)" Archived 2016-03-04 at the Wayback Machine . p. 1
3. "IMP-16 Programming and Assembler Manual" (PDF). bitsavers. National Semiconductor. Retrieved 26 December 2021.
4. "IMP-16C/200 IMP-16C/300 Microprocessors, IMP-16P Microcomputer Product Descriptions" (PDF). 1974.
5. Surdan, Esther (November 21, 1977). "Jacquard Systems Starts Small But Thinks Big". Computerworld. XI (47): 66. Retrieved 3 November 2022.
6. https://sprague.com/peter-sprague/aston-martin/ ^{[ bare URL ]}

External links

• IMP-16C board at the Selectric Typewriter Museum