PIC instruction listings

Last updated

The PIC instruction set refers to the set of instructions that Microchip Technology PIC or dsPIC microcontroller supports. The instructions are usually programmed into the Flash memory of the processor, and automatically executed by the microcontroller on startup.

Contents

PICmicro chips have a Harvard architecture and instruction words have unusual sizes. Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations. Later revisions added opcode bits, allowing additional address bits.

They are accumulator machines, with a common accumulator "W" being one operand in all 2-operand instructions.

In the instruction set tables that follow, register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (0–7) are selected by "b". Arithmetic instructions write their result to one of the inputs selected by the "d" bit: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD arithmetic.

Architecture

Memory operands are also referred to as "registers". Most are simply general-purpose storage (RAM), while some locations are reserved for special function registers. Except for a single accumulator (called W), almost all other registers are memory-mapped, even registers like the program counter and ALU status register. (The other exceptions, which are not memory-mapped, are the return address stack, and the tri-state registers used to configure the GPIO pins.)

Some arithmetic instructions only use one of their inputs, but still use a dbit. For example, MOVW copies the value of W to the destination. When used with d = 1, this stores W to f. There is a matching MOVF instruction which outputs the value of f. When used with d = 0, this loads f into W. When used with d = 1, the only visible effect is to set the zero flag depending on the value of f.

The instruction set does not contain conditional branch instructions. Instead, it contains conditional skip instructions which cause the following instruction to be ignored. A conditional skip followed by an unconditional branch performs a conditional branch. The skip instructions test any bit of any register. The ALU status register is one possibility.

Memory operands are specified by absolute address; the location is fixed at compile time. To provide indirect addressing, a pair of special function registers are provided:

This mechanism also allows up to 256 bytes of memory to be addressed, even when the instruction set only allows 5- or 7-bit absolute addresses. Models with more registers (special function registers plus RAM) than fit into the instruction provide multiple banks of memory, and use one of two mechanisms for accessing them:

  1. Most baseline core devices, and some mid-range core devices, use the high-order bits of the file select register to select the current register bank.
  2. More recent models have a separate bank select register, and a MOVLB instruction to set it.

PIC processors with more than 256 words of program use paged memory. The internal program counter and return stack are as wide as necessary to address all memory, but only the low 8 bits are visible to software in the PCL ("PC low") register. There is an additional PCLATH ("PC latch high") register which is only modified by software. Any operation which does not specify the full destination address (such as a 9-bit GOTO or an 8-bit write to the PCL register) fills in the additional high bits from the corresponding part of PCLATH. (Some PIC18 processors extend this beyond 16 bits with a PCLATU register to supply bits 16–23.)

Baseline core devices (12 bit)

This is the original 1976 instruction set, introduced in the General Instrument PIC1640 and PIC1650, [1] with the only additions since then being the miscellaneous instructions other than NOP.

12-bit PIC instruction set
1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description
0000000opcodeMiscellaneous instructions
000000000000NOPNo operation
000000000010OPTIONCopy W to OPTION register
000000000011SLEEPGo into standby mode
000000000100CLRWDTRestart watchdog timer
0000000001fTRIS fCopy W to tri-state register (f = 1, 2 or 3)
000000010kMOVLB k*Set bank select register to k
000000011110RETURN†Return from subroutine, W unmodified
000000011111RETFIE†Return from interrupt; return & enable interrupts
00opcodedregisterALU operations: dest ← OP(f,W)
0000001fMOVWF ff ← W
000001dfCLR f,dZdest ← 0, usually written CLRW or CLRF f
000010dfSUBWF f,dCZdest ← f−W (dest ← f+~W+1)
000011dfDECF f,dZdest ← f−1
000100dfIORWF f,dZdest ← f | W, logical inclusive or
000101dfANDWF f,dZdest ← f & W, logical and
000110dfXORWF f,dZdest ← f ^ W, logical exclusive or
000111dfADDWF f,dCZdest ← f+W
001000dfMOVF f,dZdest ← f
001001dfCOMF f,dZdest ← ~f, bitwise complement
001010dfINCF f,dZdest ← f+1
001011dfDECFSZ f,ddest ← f−1, then skip if zero
001100dfRRF f,dCdest ← CARRY<<7 | f>>1, rotate right through carry
001101dfRLF f,dCdest ← F<<1 | CARRY, rotate left through carry
001110dfSWAPF f,ddest ← f<<4 | f>>4, swap nibbles
001111dfINCFSZ f,ddest ← f+1, then skip if zero
01opcbitregisterBit operations
0100bitfBCF f,bClear bit b of f
0101bitfBSF f,bSet bit b of f
0110bitfBTFSC f,bSkip if bit b of f is clear
0111bitfBTFSS f,bSkip if bit b of f is set
10opckControl transfers
1000kRETLW kSet W ← k, then return from subroutine
1001kCALL kCall subroutine, 8-bit address k
101kGOTO kJump to 9-bit address k [2]
11opc8-bit immediateOperations with W and 8-bit literal: W ← OP(k,W)
1100kMOVLW kW ← k
1101kIORLW kZW ← k | W, bitwise logical or
1110kANDLW kZW ← k & W, bitwise and
1111kXORLW kZW ← k ^ W, bitwise exclusive or
1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description

*: Extended instruction, not available on most 12-bit PICs. Of the models with extended RAM, most (e.g. 16C5x, 16F5x) extend the register address space using the high-order bits of the FSR. A few (e.g. PIC12F529T39A) have a separate bank select register which can be set with this instruction.
†: Extended instruction, only available on "enhanced baseline" PICs. Only the very few models (16F527, 16F570, MCV20A) with interrupt support (and a 4-level stack) include these instructions. All such models also include MOVLB.

General Instrument PIC1670 (13 bit, obsolete)

Introduced in 1979, this expanded PIC supported 64 bytes of register space (16 special function registers and 48 bytes of RAM), 1024 words of ROM, a 6-level hardware stack, and interrupt handling. The PIC1665 was a variant with external ROM used for developing firmware for the mask ROM 1670.

It added a signed overflow bit to the status register (bit 3). Status register bits 4 and 5 provided read-only access to the high 2 bits of the 10-bit program counter.

The instruction set is mostly the same as the 12-bit PIC with the address field enlarged. However, the 8-bit immediate instructions gain an additional opcode bit. Rather than adding an additional four instructions with an 8-bit immediate operand, the instruction set adds two instructions with 8-bit operands, two instructions with 7-bit operands (6-bit address plus direction bit), and four instructions with 6-bit operands (6-bit address):

This instruction set is not used in any currently manufactured part and is of historical interest only.

13-bit PIC1670 instruction set (obsolete) [3]
1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description
0000000opcodeMiscellaneous instructions
0000000000000NOPNo operation
0000000000001HALTHalt processor (PIC1665 only)
0000000000010RETFIReturn from interrupt
0000000000011RETFSReturn from subroutine, W unmodified
0000000000100DAWDecimal Adjust W
00opcodedregisterALU operations same as 12- and 14-bit PIC except
000001dfSUBBWF f,dCZdest ← f−W−C = f+~W+C (not CLR f,d)
001000dfADCWF f,dCZdest ← f+W+C (not MOVF f,d)
01opcbitregisterBit operations same as 12- and 14-bit PIC
1000opcoderegisterAdditional ALU operations, no choice of destination
1000000fMOVFW fZW ← f (= MOVF f,0)
1000001fCLRF fZf ← 0 (for CLRW, use MOVLW 0)
1000010fRRNC ff ← f<<7 | f>>1, rotate right no carry
1000011fRLNC ff ← f<<1 | f>>7, rotate left no carry
1000100fCPFSLT fCompare and skip if f < W (unsigned)
1000101fCPFSEQ fCompare and skip if f = W
1000110fCPFSGT fCompare and skip if f > W (unsigned)
1000111fTESTF fZf ← f (= MOVF f,1)
10opcode8-bit immediateOperations with W and 8-bit literal: W ← OP(k,W)
10010kMOVLW kW ← k
10011kADDLW kCZW ← k+W
10100kIORLW kZW ← k | W, bitwise logical or
10101kANDLW kZW ← k & W, bitwise and
10110kXORLW kZW ← k ^ W, bitwise exclusive or
10111kRETLW kW ← k, then return from subroutine
11ckControl transfers
110kGOTO kJump to address k
111kCALL kCall subroutine
1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description

ELAN Microelectronics clones (13 bit)

ELAN Microelectronics Corp. make a series of PICmicro-like microcontrollers with a 13-bit instruction word. [4] The instructions are mostly compatible with the mid-range 14-bit instruction set, but limited to a 6-bit register address (16 special-purpose registers and 48 bytes of RAM) and a 10-bit (1024 word) program space.

The 10-bit program counter is accessible as R2. Reads access only the low bits, and writes clear the high bits. An exception is the TBL instruction, which modifies the low byte while preserving bits 8 and 9.

The 7 accumulator-immediate instructions are renumbered relative to the 14-bit PICmicro, to fit into 3 opcode bits rather than 4, but they are all there, as well as an additional software interrupt instruction.

There are a few additional miscellaneous instructions, and there are some changes to the terminology (the PICmicro OPTION register is called the CONTrol register; the PICmicro TRIS registers 1–3 are called I/O control registers 5–7), but the equivalents are obvious.

13-bit EM78 instruction set [5] [6]
1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description
0000000opcodeMiscellaneous instructions
0000000000000NOP*No operation
0000000000001DAA†C Decimal Adjust after Addition
0000000000010CONTW*Write CONT register (CONT ← W)
0000000000011SLEP*Go into standby mode (WDT ← 0, stop clock)
0000000000100WDTC*Restart watchdog timer (WDT ← 0)
000000000fIOW f†Copy W to I/O control register (f = 5–7, 11–15)
0000000010000ENI†Enable interrupts
0000000010001DISI†Disable interrupts
0000000010010RETReturn from subroutine, W unmodified
0000000010011RETIReturn from interrupt; return & enable interrupts
0000000010100CONTR†Read CONT register (W ← CONT)
000000001fIOR f†Copy I/O control register to W (f = 5–7, 11–15)
0000000100000TBL†CZPCL += W, preserve PC bits 8 & 9
00opcodedregisterALU operations same as 12- and 14-bit PIC
01opcbitregisterBit operations same as 12- and 14-bit PIC
10ckControl transfers same as 14-bit PIC
11opcode8-bit immediateOperations with W and 8-bit literal: W ← OP(k,W)
110opkMOV/IOR/AND/XOR, same as 12-bit PIC
11100kRETLW kW ← k, then return from subroutine
11101kSUBLW kCZW ← k−W (W ← k+~W+1)
111100kINT k†Push PC, PC ← k (software interrupt, usually k=1)
11111kADDLW kCZW ← k+W
111101opcodekExtensions (replacing INT k for k≥128 on later models) [6] [7] [8]
111101000kPAGE kSelect ROM page k (like MOVLP k)
111101001kBANK k†Select RAM bank k
111101010kLCALL k†Long call with 17-bit address (2-word instruction)
111101011kLJMP k†Long jump with 17-bit address (2-word instruction)
1111011fTBRD f†Read ROM at TBHP:TBLP into specified register
1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description

*: Same opcode as 12-bit PIC
†: Instruction unique to EM78 instruction set with no PIC equivalent

Some models support multiple ROM or RAM banks, in a manner similar to other PIC microcontrollers.

There is also a 15-bit variant of the instruction set, which is almost identical except that the register numbers are enlarged to 8 bits and the call and jump addresses are enlarged to 12 bits. Other differences: [9]

A second generation 15-bit instruction set includes several additional instructions:

15-bit EM78/EM88 instruction set extensions [10] [11]
1
4		1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description
00000000opcodeMiscellaneous instructions
000000000000000NOP*No operation
000000000000001DAA*C Decimal Adjust after Addition
000000000000011SLEP*Go into standby mode (WDT ← 0, stop clock)
000000000000100WDTC*Restart watchdog timer (WDT ← 0)
000000000000101MULW†8×8 → 16-bit multiply
000000000000110DIVW†8÷8 → 8,8-bit divide
000000000010000ENI*Enable interrupts
000000000010001DISI*Disable interrupts
000000000010010RET*Return from subroutine, W unmodified
000000000010011RETI*Return from interrupt; return & enable interrupts
000000000010110RESETSoftware reset
000000000010111TBWRFlash ROM write
000000001kINT kSoftware interrupt at address 2×k
00000001bitfBTG f,bInvert (toggle) bit b of f (limited address range)
00opcodedregisterALU operations same as EM78 and PIC
01opcbitregisterBit operations same as EM78 and PIC
10ckControl transfers same as EM78 and 14-bit PIC
11opcode008-bit immediateOperations with 8-bit literal same as EM78 (except INT)
11opcoderegister or immediateInstruction set extensions
1100001fJE rSkip if W = f
1100010fJGE rSkip if W > f
1100011fJLE rSkip if W < f
1100101kJE kSkip if W = k
1100110k(reserved)
1100111fTBRDA fRead ROM at TBHP:TBLP into f; msbits into W
1101001kSJC addressJump to PC + sext(k) if carry set
1101010kSJNC addressJump to PC + sext(k) if carry clear
1101011kSJZ addressJump to PC + sext(k) if zero flag set
1101101kSJNZ addressJump to PC + sext(k) if zero flag clear
110111dfRR f/RRAdest ← f<<7 | f>>1, rotate right without carry
1110001fXCH fExchange f ↔ W
111001dfRL f/RLAdest ← f<<1 | f>>7, rotate left without carry
1110101fMUL f‡PRODH:PRODL ← f × W
111011xk(reserved)
111100dfSUBBCZdest ← f + ~W + C, subtract with carry
11110100000kSBANK k*Select special function register bank k
11110100100kGBANK k*Select RAM bank k
11110101000kLCALL k*Long call with 19-bit address (2-word instruction)
11110101100kLJMP k*Long jump with 19-bit address (2-word instruction)
1111011fTBRD f*Read ROM at TBHP:TBLP into f
1111101fNEG fCZf ← −f (f ← ~f + 1), negate
111111dfADC fCZdest ← f + W + C, add with carry

*: Same opcode as 13-bit EM78
†: Only on EM89F768N; operands and results in special registers
‡: Only on EM88F794N, MTF213 and MTF351

Mid-range core devices (14 bit)

These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack. The instruction set differs very little from the baseline devices, but the 2 additional opcode bits allow 128 registers and 2048 words of code to be directly addressed. There are a few additional miscellaneous instructions, and two additional 8-bit literal instructions, add and subtract. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.

14-bit PIC instruction set
1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description
0000000opcodeMiscellaneous instructions
00000000000000NOPNo operation
00000000001000RETURNReturn from subroutine, W unmodified
00000000001001RETFIEReturn from interrupt
00000001100010OPTIONCopy W to OPTION register (deprecated)
00000001100011SLEEPGo into standby mode
00000001100100CLRWDTRestart watchdog timer
000000011001fTRIS fCopy W to tri-state register (f = 1, 2 or 3) (deprecated)
00opcodedregisterALU operations: dest ← OP(f,W)
0000001fMOVWF ff ← W
000001dfCLR f,dZdest ← 0, usually written CLRW or CLRF f
000010dfSUBWF f,dCZdest ← f−W (dest ← f+~W+1)
000011dfDECF f,dZdest ← f−1
000100dfIORWF f,dZdest ← f | W, logical inclusive or
000101dfANDWF f,dZdest ← f & W, logical and
000110dfXORWF f,dZdest ← f ^ W, logical exclusive or
000111dfADDWF f,dCZdest ← f+W
001000dfMOVF f,dZdest ← f
001001dfCOMF f,dZdest ← ~f, bitwise complement
001010dfINCF f,dZdest ← f+1
001011dfDECFSZ f,ddest ← f−1, then skip if zero
001100dfRRF f,dCdest ← CARRY<<7 | f>>1, rotate right through carry
001101dfRLF f,dCdest ← f<<1 | CARRY, rotate left through carry
001110dfSWAPF f,ddest ← f<<4 | f>>4, swap nibbles
001111dfINCFSZ f,ddest ← f+1, then skip if zero
01opcbitregisterBit operations
0100bitfBCF f,bClear bit b of f
0101bitfBSF f,bSet bit b of f
0110bitfBTFSC f,bSkip if bit b of f is clear
0111bitfBTFSS f,bSkip if bit b of f is set
10ckControl transfers
100kCALL kCall subroutine
101kGOTO kJump to address k
11opcode8-bit immediateOperations with W and 8-bit literal: W ← OP(k,W)
1100xxkMOVLW kW ← k
1101xxkRETLW kW ← k, then return from subroutine
111000kIORLW kZW ← k | W, bitwise logical or
111001kANDLW kZW ← k & W, bitwise and
111010kXORLW kZW ← k ^ W, bitwise exclusive or
111011k(reserved)
11110xkSUBLW kCZW ← k−W (dest ← k+~W+1)
11111xkADDLW kCZW ← k+W
1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description

Enhanced mid-range core devices (14 bit)

Enhanced mid-range core devices introduce a deeper hardware stack, additional reset methods, 14 additional instructions and C programming language optimizations. [12] In particular. there are two INDF registers (INDF0 and INDF1), and two corresponding FSR register pairs (FSRnL and FSRnH). Special instructions use FSRn registers like address registers, with a variety of addressing modes.

14-bit enhanced PIC additional instructions
1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description
0000000opcodeMiscellaneous instructions
00000000000001RESETSoftware reset
00000000001010CALLWPush PC, then jump to PCLATH:W
00000000001011BRWPC ← PC + W, relative jump using W
00000000010n00MOVIW ++FSRnZIncrement FSRn, then W ← INDFn
00000000010n01MOVIW −−FSRnZDecrement FSRn, then W ← INDFn
00000000010n10MOVIW FSRn++ZW ← INDFn, then increment FSRn
00000000010n11MOVIW FSRn−−ZW ← INDFn, then decrement FSRn
00000000011nmMOVWI using FSRnINDFn ← W, same modes as MOVIW
000000001kMOVLB kBSR ← k, move literal to bank select register
11opcodedregisterALU operations: dest ← OP(f,W)
110101dfLSLF f,dCZdest ← f << 1, logical shift left
110110dfLSRF f,dCZdest ← f >> 1, logical shift right
110111dfASRF f,dCZdest ← f >> 1, arithmetic shift right
111011dfSUBWFB f,dCZdest ← f + ~W + C, subtract with carry
111101dfADDWFC f,dCZdest ← f + W + C, add with carry
11opcodekOperations with literal k
1100010nkADDFSR FSRn,kFSRn ← FSRn + k, add 6-bit signed offset
1100011kMOVLP kPCLATH ← k, move 7-bit literal to PC latch high
11001kBRA kPC ← PC + k, branch relative using 9-bit signed offset
1111110nkMOVIW k[FSRn]ZW ← [FSRn+k], 6-bit signed offset
1111111nkMOVWI k[FSRn][FSRn+k] ← W, 6-bit signed offset
1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description

Holtek clones (14, 15 or 16 bit)

Holtek make numerous 8-bit microcontrollers with a 14-bit instruction word equivalent to the (non-enhanced) mid-range core. The instruction encodings all fit into 14 bits and provide 7-bit operand addresses.

The instruction format is identical to Microchip's, but the opcodes are assigned in a different order, and the manufacturer uses different instruction mnemonics. The accumulator is called ACC rather than W, and the destination is specified by a suffix to the instruction mnemonic rather than an operand. (Instructions which do not use the accumulator by default write back to memory, and use an A suffix to indicate the destination is the accumulator. Two-operand instructions by default write to the accumulator, and use an M suffix to indicate a memory destination.)

In addition to the different opcode assignment, there are semantic differences in a few instructions:

Several operations have been added to the 14-bit PICmicro repertoire:

15-bit models use bit 14 of the instruction as an 8th operand address bit and a 12th CALL/JMP target address bit. 16-bit models add a 13th CALL/JMP target address bit, but do not add a 9th operand addresses bit. [14]

Instead, some 16-bit models support an extended instruction set. This adds a few new instructions (skip on byte without inc/decrement, subtract immediate with carry, ROM read with address increment), but also adds 2-word "long" variants of all memory instructions. When bit 15 of the opcode is set, it indicates that the 8-bit operand address in opcode bits 0–6 and 14 is extended to 16 bits using bits 0–7 of the following instruction word. Such instructions are written with an L prefix (LADD vs. ADD) and take an extra cycle to execute. [13]

14-bit Holtek instruction set [15]
1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicPIC
equivalent		C
?		Z
?		Description
00000000000opcodeMiscellaneous instructions
00000000000000NOPNOPNo operation
00000000000001CLR WDT1CLRWDTRestart watchdog timer
00000000000010HALTSLEEPGo into low-power mode
00000000000011RETRETURNReturn from subroutine
00000000000100RETIRETFIEReturn from interrupt
00000000000101CLR WDT2≈CLRWDTRestart watchdog timer
0000000000011x(reserved)
0000000≠0xxx(reserved)
000opcodedaddressALU operations part 1: dest ← OP(ACC,[m])*
0000001mMOV [m],AMOVWF m[m] ← ACC
000001dmCPLA/CPL [m]COMF m,dZdest ← ~[m], bitwise complement
000010dmSUB/SUBM A,[m]≠SUBWF m,dCZdest ← ACC − [m] (dest ← ACC+~[m]+1)
000011dmADD/ADDM A,[m]ADDWF m,dCZdest ← ACC + [m]
000100dmXOR/XORM [m]XORWF m,dZdest ← ACC ^ [m], logical exclusive or
000101dmOR/ORM [m]IORWF m,dZdest ← ACC | [m], logical inclusive or
000110dmAND/ANDM [m]ANDWF m,dZdest ← ACC & [m], logical and
0001110mMOV A,[m]≈MOVF m,0ACC ← [m]
0001111m—≈MOVF m,1[m] ← [m]
001opcode8-bit immediateOperations with 8-bit literal: ACC ← OP(ACC,k)
001000kSBC A,k†—CZACC ← ACC + ~[m] + C, subtract with carry
001001kRET A,kRETLW kACC ← k, then return from subroutine
001010kSUB A,k≠SUBLW kCZACC ← ACC − k (ACC ← ACC+~k+1)
001011kADD A,kADDLW kCZACC ← ACC + k
001100kXOR A,kXORLW kZACC ← ACC ^ k, logical exclusive or
001101kOR A,kIORLW kZACC ← ACC | k, logical inclusive or
001110kAND A,kANDLW kZACC ← ACC & k, logical and
001111kMOV A,kMOVLW kACC ← k
01opcodedaddressALU operations part 2: dest ← OP(ACC,[m])*
010000dmSZA/SZ [m]—dest ← [m], skip next instruction if zero
010001dmSWAPA/SWAP [m]SWAPF m,ddest ← [m]<<4 | [m]>>4, swap nibbles
010010dmSBC/SBCM A,[m]≠SUBWFB m,dCZdest ← ACC + ~[m] + C, subtract with carry
010011dmADC/ADCM A,[m]ADDWFC m,dCZdest ← ACC + [m] + C, add with carry
010100dmINCA/INC [m]INCF m,dZdest ← [m] + 1
010101dmDECA/DEC [m]DECF m,dZdest ← [m] − 1
010110dmSIZA/SIZ [m]INCFSZ m,ddest ← [m] + 1, then skip if zero
010111dmSDZA/SDZ [m]DECFSZ m,ddest ← [m] − 1, then skip if zero
011000dmRLA/RL [m]—dest ← [m] << 1 | [m] >> 7, rotate left 1 bit
011001dmRRA/RR [m]—dest ← [m] << 7 | [m] >> 1, rotate right 1 bit
011010dmRLCA/RLC [m]RLF m,dCdest ← [m] << 1 | C, rotate left through carry
011011dmRRCA/RRC [m]RRF m,dCdest ← C << 7 | [m] >> 1, rotate right through carry
0111opcodeaddressSpecial operations: [m] ← special*
0111000mITABRD [m]†—TBLH:[m] ← ROM[TBHP:++TBLP], with pre-increment
0111001mITABRDL [m]†—TBLH:[m] ← ROM[0xff:++TBLP], with pre-increment
0111010mTABRD [m]—TBLH:[m] ← ROM[TBHP:TBLP], table lookup
0111011mTABRDL [m]—TBLH:[m] ← ROM[0xff:TBLP], read from last page of ROM
0111100mSNZ [m]†—[m] ← [m], skip next instruction if non-zero
0111101mDAA [m]—C[m] ← DAA(ACC), decimal adjust after BCD addition
0111110mCLR [m]≈CLRF m[m] ← 0
0111111mSET [m]—[m] ← 255
10ckControl transfers
100kCALL kCALL kCall subroutine
101kJMP kGOTO kJump to address k
11opcbitaddressBit operations*
1100bitmSET [m].bBSF m,bSet bit b of [m]
1101bitmCLR [m].bBCF m,bClear bit b of [m]
1110bitmSNZ [m].bBTFSS m,bSkip if bit b of [m] is set
1111bitmSZ [m].bBTFSC m,bSkip if bit b of [m] is clear
1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicPIC
equivalent		C
?		Z
?		Description

*: Instructions available in long forms on 16-bit models with extended instruction set.
†: Instruction only available on 16-bit models with extended instruction set.

Padauk microcontrollers (13, 14, 15 or 16 bit)

Padauk Technology make a series of PIC-like microcontrollers notable for their extremely low cost, beginning at US$0.033 in quantity, [16] with many models costing less than US$0.10. [17] [18] [19]

Although clearly derived from the Microchip PIC12 series, [17] [20] there are some significant differences:

13-bit Padauk instruction set [21] [22]
1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicPIC
equivalent		C
?		Z
?		Description
000000000opcodeMiscellaneous instructions
0000000000000NOPNOPNo operation
0000000000001(reserved)
000000000001x(reserved)
000000000010x(reserved)
0000000000110LDSPTL—A ← ROM[[SP]], load low/high byte of ROM word using 16-bit pointer on top of stack
0000000000111LDSPTH—
0000000001—(reserved)
000000001opcodeOne-operand instructions on accumulator
Same as one-operand instructions on memory (below) except
0000000010111PCADD A≈ADDWF PCL,1PC ← PC + A, add to program counter (not XCH A)
0000000011110SWAP A—A ← A<<4 | A>>4, swap nibbles (not CEQSN A)
000000010—(reserved)
000000011opcodeSystem control instructions
0000000110000WDRESETCLRWDTRestart watchdog timer
0000000110001(reserved)
0000000110010PUSHAF—Push A then flags on top of stack
0000000110011POPAF—CZPop flags then A from top of stack
0000000110100(reserved)
0000000110101RESETRESETSoftware reset
0000000110110STOPSYSSLEEPGo into standby mode (clock stopped)
0000000110111STOPEXE—Go into standby mode (clock running)
0000000111000ENGINTBSF INTCON,GIEEnable interrupts
0000000111001DISGINTBCF INTCON,GIEDisable interrupts
0000000111010RETRETURNReturn from subroutine, A unmodified
0000000111011RETIRETFIEReturn from interrupt
0000000111100MUL—MULRH:A ← A × MULOP (not all models)
0000000111101(reserved)
000000011111x(reserved)
00000opcodeioaddrByte-wide I/O operations
00000011ioaddrXOR ioaddr,A—IO[ioaddr] ← A ^ IO[address]
00000100ioaddrMOV ioaddr,A—IO[ioaddr] ← A
00000101ioaddrMOV A,ioaddr—ZA ← IO[ioaddr]
0000011caddressc16-bit operations (RAM address limited, even)
00000110address0STT16 addr—Timer16 ← [address]
00000110address1LDT16 addr—[address] ← Timer16
00000111address0IDXM addr,A—[[address]] ← A, indirect memory address
00000111address1IDXM A,addr—A ← [[address]], indirect memory address
00001kReturn literal constant
00001kRET kRETLW kA ← k, then return from subroutine
0001cbitcaddressBit operations with RAM (first 16 bytes only)
00010bit0addressT0SN addr.bBTFSC addr,bSkip if bit b of [addr] is clear
00010bit1addressT1SN addr.bBTFSS addr,bSkip if bit b of [addr] is set
00011bit0addressSET0 addr.bBCF addr,bClear bit b of [addr]
00011bit1addressSET1 addr.bBSF addr,bSet bit b of [addr]
001dopcodeaddressALU operations between A and memory
0010000addressADD addr,AADDWF addr,1CZ[addr] ← [addr] + A
0010001addressSUB addr,ASUBWF addr,1CZ[addr] ← [addr] − A
0010010addressADDC addr,AADDWFC addr,1CZ[addr] ← [addr] + A + C
0010011addressSUBC addr,A≈SUBWFB addr,1CZ[addr] ← [addr] − A − C
0010100addressAND addr,AANDWF addr,1Z[addr] ← [addr] & A, logical and
0010101addressOR addr,AIORWF addr,1Z[addr] ← [addr] | A, logical inclusive or
0010110addressXOR addr,AXORWF addr,1Z[addr] ← [addr] ^ A, logical exclusive or
0010111addressMOV addr,AMOVWF addr[addr] ← A
0011000addressADD A,addrADDWF addr,0CZA ← A + [addr]
0011001addressSUB A,addr≠SUBWF addr,0CZA ← A − [addr]
0011010addressADDC A,addrADDWFC addr,0CZA ← A + [addr] + C
0011011addressSUBC A,addr≠SUBWFB addr,0CZA ← A − [addr] − C
0011100addressAND A,addrANDWF addr,0ZA ← [A] & [addr], logical and
0011101addressOR A,addrIORWF addr,0ZA ← A | [addr], logical inclusive or
0011110addressXOR A,addrXORWF addr,0ZA ← A ^ [addr], logical exclusive or
0011111addressMOV A,addrMOVF addr,0ZA ← [addr]
010opcodeaddressOne-operand operations on memory
0100000addressADDC addr—CZ[addr] ← [addr] + C
0100001addressSUBC addr—CZ[addr] ← [addr] − C
0100010addressIZSN addrINCFSZ addr,1CZ[addr] ← [addr] + 1, then skip if zero
0100011addressDZSN addrDECFSZ addr,1CZ[addr] ← [addr] − 1, then skip if zero
0100100addressINC addrINCF addr,1CZ[addr] ← [addr] + 1
0100101addressDEC addrDECF addr,1CZ[addr] ← [addr] − 1
0100110addressCLEAR addr≈CLRF addr[addr] ← 0
0100111addressXCH addr—A ← [addr], [addr] ← A
0101000addressNOT addrCOMF addr,1Z[addr] ← ~[addr], bitwise complement
0101001addressNEG addr—Z[addr] ← −[addr], negate
0101010addressSR addr≈LSRF addr,1C[addr] ← [addr] >> 1, logical shift right
0101011addressSL addr≈LSLF addr,1C[addr] ← [addr] << 1, shift left
0101100addressSRC addrRRF addr,1C[addr] ← C << 7 | [addr] >> 1, rotate right through carry
0101101addressSLC addrRLF addr,1C[addr] ← [addr] << 1 | C, rotate left through carry
0101110addressCEQSN addr—CZCompute A − [addr], then skip if zero
0101111address(reserved for CNEQSN)
011opcbitaddressBit operations with I/O
01100bitaddressT0SN ioaddr.bBTFSC ioaddr,bSkip if bit b of [ioaddr] is clear
01101bitaddressT1SN ioaddr.bBTFSS ioaddr,bSkip if bit b of [ioaddr] is set
01110bitaddressSET0 ioaddr.bBCF ioaddr,bClear bit b of [ioaddr]
01111bitaddressSET1 ioaddr.bBSF ioaddr,bSet bit b of [ioaddr]
10opcodeliteralLiteral operations: A ← OP(A,k)
10000kADD A,kADDLW kCZA ← A + k
10001kSUB A,k≠SUBLW kCZA ← A − k
10010kCEQSN A,k—CZCompute A − k, then skip if zero
10011k(reserved for CNEQSN)
10100kAND A,k≈ANDLW kZA ← A & k
10101kOR A,k≈IORLW kZA ← A | k
10110kXOR A,k≈XORLW kZA ← A ^ k
10111kMOV A,kMOVLW kA ← k
11ckControl transfers: PC ← k
110kGOTO kGOTO kPC ← k
111kCALL kCALL kPush PC, then PC ← k
1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicPIC
equivalent		C
?		Z
?		Description

The 14-, 15- and 16-bit instruction sets primarily differ in having wider address fields, although some encoding changes are made to allow a few additional instructions (such as CNEQSN, which performs a compare and skip if not equal.)

14-bit Padauk instruction set [23] [24]
1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicPIC
equivalent		C
?		Z
?		Description
0000000000opcodeMiscellaneous instructions same as 13-bit
0000000001—(reserved)
000000001—(reserved)
000000010—(reserved)
0000000110opcodeOne-operand instructions on A same as 13-bit
0000000111opcodeSystem control instructions same as 13-bit
00000010—(reserved)
00000opcodeaddressByte-wide I/O operations same as 13-bit, but opcodes changed
00000011ioaddrXOR ioaddr,A—IO[ioaddr] ← A ^ IO[address]
0000010—(reserved)
00000110ioaddrMOV ioaddr,A—IO[ioaddr] ← A
00000111ioaddrMOV A,ioaddr—ZA ← IO[ioaddr]
000010kReturn literal constant same as 13-bit
000011caddressc16-bit operations same as 13-bit, but 128-byte range
00010bitaddressCopy bit to I/O
00010bitaddressSWAPC ioaddr.b—CSwap carry with [ioaddr] bit b
00011cdaddressAdditional 2-operand operations
0001100addressCOMP A,addr—CZA − [addr], flags set, result discarded
0001101addressCOMP addr,A—CZ[addr] − A, flags set, result discarded
0001110addressNADD A,addrSUBWF addr,0CZA ← [addr] + −A (A ← [addr] + ~A + 1)
0001111addressNADD addr,A—CZ[addr] ← A + −[addr] ([addr] ← A + ~[addr] + 1)
001dopcodeaddress2-operand instructions same as 13-bit
010opcodeaddressOne-operand operations on memory same as 13-bit, plus CNEQSN
0101111addressCNEQSN addr—CZCompute A − [addr], then skip if non-zero
011opcbitioaddrBit operations with I/O same as 13-bit, but 64-byte range
100opcbitaddressBit operations with memory same as 13-bit, but 64-byte range
101opcodeliteralLiteral operations same as 13-bit, plus CNEQSN
101011kCNEQSN A,k—CZCompute A − k, then skip if non-zero
11ckControl transfers same as 13-bit
1
13		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicPIC
equivalent		C
?		Z
?		Description

PIC18 high end core devices (16 bit)

In 2000, Microchip introduced the PIC18 architecture. Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language. [25]

The PIC18 has a 12-bit RAM address space, divided into 16 pages of 256 bytes. The 8-bit f field determines the address in combination with the a bit and the 4-bit bank select register (BSR). If a=0, the BSR is ignored and the f field is sign-extended to the range 0x000–0x07F (global RAM) or 0xF80–0xFFF (special function registers). If a=1, the f field is extended with the BSR to generate the 12-bit address.

The PIC18 extends the FSR/INDF mechanism used in previous PICmicro processors for indirect addressing in two ways:

First, it provides three file select registers. The FSRn registers are 12 bits long (each split into two 8-bit portions FSR0L through FSR2H), and access to the corresponding INDFn register (INDF0 through INDF2) acts as an alias for the addressed byte.

Second, there are addressing modes. For each of the three, there is not just one INDFn register, but five, and the one used determines the addressing mode:

There are also instructions to directly load an FSR pair with a 12-bit address, and a MOVFF instruction that moves a byte between two 12-bit addresses.

PIC18 16-bit instruction set [26]
1
5		1
4		1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		N
?		Description
00000000opcodeMiscellaneous instructions
0000000000000000NOPNo operation
0000000000000011SLEEPGo into standby mode
0000000000000100CLRWDTRestart watchdog timer
0000000000000101PUSHPush PC on top of stack
0000000000000110POPPop (and discard) top of stack
0000000000000111DAWCDecimal adjust W
0000000000001000TBLRD∗Table read: TABLAT ← mem[TBLPTR]
0000000000001001TBLRD∗+Table read with postincrement
0000000000001010TBLRD∗−Table read with postdecrement
0000000000001011TBLRD+∗Table read with pre-increment
00000000000011modTBLWRTable write, same modes as TBLRD
000000000001000sRETFIE [, FAST]Return from interrupt
000000000001001sRETURN [, FAST]Return from subroutine
0000000000010100CALLW*Push PC, jump to PCLATU:PCLATH:W
0000000011111111RESET000Software reset
00000001—0—kMOVLBMove literal k to bank select register
00001opcodeliteralLiteral operations: W ← OP(k,W)
00001000kSUBLW kW ← k − W
00001001kIORLW kW ← k | W, logical inclusive or
00001010kXORLW kW ← k ^ W, exclusive or
00001011kANDLW kW ← k & W, logical and
00001100kRETLW kRETURN W ← k
00001101kMULLW kW ← k × W
00001110kMOVLW kW ← k
00001111kADDLW kW ← k + W
0opcodedaregisterALU operations: dest ← OP(f,W)
0000001afMULWF f,aPRODH:PRODL ← W × f (unsigned)
000001dafDECF f,d,aCZNdest ← f − 1
000100dafIORWF f,d,aZNdest ← f | W, logical inclusive or
000101dafANDWF f,d,aZNdest ← f & W, logical and
000110dafXORWF f,d,aZNdest ← f ^ W, exclusive or
000111dafCOMF f,d,aZNdest ← ~f, bitwise complement
001000dafADDWFC f,d,aCZNdest ← f + W + C
001001dafADDWF f,d,aCZNdest ← f + W
001010dafINCF f,d,aCZNdest ← f + 1
001011dafDECFSZ f,d,adest ← f − 1, skip if 0
001100dafRRCF f,d,aCZNdest ← f>>1 | C<<7, rotate right through carry
001101dafRLCF f,d,aCZNdest ← f<<1 | C, rotate left through carry
001110dafSWAPF f,d,adest ← f<<4 | f>>4, swap nibbles
001111dafINCFSZ f,d,adest ← f + 1, skip if 0
010000dafRRNCF f,d,aZNdest ← f>>1 | f<<7, rotate right (no carry)
010001dafRLNCF f,d,aZNdest ← f<<1 | f>>7, rotate left (no carry)
010010dafINFSNZ f,d,adest ← f + 1, skip if not 0
010011dafDCFSNZ f,d,adest ← f − 1, skip if not 0
010100dafMOVF f,d,aZNdest ← f
010101dafSUBFWB f,d,aCZNdest ← W + ~f + C (dest ← W − f − C̅)
010110dafSUBWFB f,d,aCZNdest ← f + ~W + C (dest ← f − W − C̅)
010111dafSUBWF f,d,aCZNdest ← f − W (dest ← f + ~W + 1)
0110opcodearegisterALU operations, do not write to W
0110000afCPFSLT f,askip if f < W (unsigned)
0110001afCPFSEQ f,askip if f == W
0110010afCPFSGT f,askip if f > W (unsigned)
0110011afTSTFSZ f,askip if f == 0
0110100afSETF f,af ← 0xFF
0110101afCLRF f,a1f ← 0, PSR.Z ← 1
0110110afNEGF f,aCZNf ← −f
0110111afMOVWF f,af ← W
0111bitafBTG f,b,aToggle bit b of f
10opcbitaregisterBit operations
1000bitafBSF f,b,aSet bit b of f
1001bitafBCF f,b,aClear bit b of f
1010bitafBTFSS f,b,aSkip if bit b of f is set
1011bitafBTFSC f,b,aSkip if bit b of f is clear
110opcaddressLarge-address operations
1100sourceMOVFF s,dMove absolute
1111destination
11010nBRA nBranch to PC + 2n
11011nRCALL nSubroutine call to PC + 2n
11100condnConditional branch (to PC+2n)
11100000nBZ nBranch if PSR.Z is set
11100001nBNZ nBranch if PSR.Z is clear
11100010nBC nBranch if PSR.C is set
11100011nBNC nBranch if PSR.C is clear
11100100nBOV nBranch if PSR.V is set
11100101nBNOV nBranch if PSR.V is clear
11100110nBN nBranch if PSR.N is set
11100111nBNN nBranch if PSR.N is clear
111010opckExtensions for using FSR2 as software stack pointer*
11101000nkADDFSR n,k*FSRn += k
1110100011kADDULNK k*FSR2 += k, pop PC
11101001nkSUBFSR n,k*FSRn −= k
1110100111kSUBULNK k*FSR2 −= k, pop PC
11101010kPUSHL k*[FSR2] ← k, decrement FSR2
111010110sMOVSF src,f *f ← FSR2[s]
1111f
111010111sMOVSS src,dst*FSR2[d] ← FSR2[s]
1111—0—d
111011opck2-word instructions
1110110sk (lsbits)CALL k[, FAST]Call subroutine (20-bit address)
1111k (msbits)
1110111000fk (msb)LFSR f,kMove 12-bit literal to FSRf
11110000k (lsbits)
11101111k (lsbits)GOTO kAbsolute jump, PC ← k (20-bit address)
1111k (msbits)
1111kNo operation, second word of 2-word instructions
1
5		1
4		1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		N
?		Description

*: These extended instructions are only available on some models, and then only if the XINST configuration bit is set.

PIC24 and dsPIC 16-bit microcontrollers

In 2001, Microchip introduced the dsPIC series of chips, [27] which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include digital signal processing capabilities in addition.

Instructions come in two main varieties. One is like the classic one-operand PIC instructions, with an operation between W0 and a value in a specified f register (i.e. the first 8K of RAM), and a destination select bit selecting which is updated with the result. The W registers are memory-mapped, so the f operand may specify a W register.

The other form, new to the PIC24, specifies three W register operands, two of which allow a 3-bit addressing mode specification:

PIC24 addressing modes
source operanddestination operandDescription
pppRegSyntaxqqqRegSyntax
000ssssWs000ddddWdRegister direct
001ssss[Ws]001dddd[Wd]Indirect
010ssss[Ws−−]010dddd[Wd−−]Indirect with postdecrement
011ssss[Ws++]011dddd[Wd++]Indirect with postincrement
100ssss[−−Ws]100dddd[−−Wd]Indirect with predecrement
101ssss[++Ws]101dddd[++Wd]Indirect with preincrement
11kkkkk#u5(Unused, illegal)5-bit unsigned immediate
11xssss[Ws+Ww]11xdddd[Wd+Ww]Indirect with register offset

The register offset addressing mode is only available for the MOV src,dst instruction, where the Ww register may be used as a register offset for the source, destination, or both. All other instructions use this encoding for an unsigned 5-bit immediate source instead.

For the operands to TBLRD and TBLWT which access program memory, only the indirect modes are allowed, and refer to addresses in code memory.

A few instructions are 2 words long. The second word is a NOP, which includes up to 16 bits of additional immediate operand.

PIC24 24-bit instruction set [28]
2
3		2
2		2
1		2
0		1
9		1
8		1
7		1
6		1
5		1
4		1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		N
?		Description
0000opcodeoffsetControl transfers
00000000—NOPNo operation
00000000—0—n<22:16>CALL/GOTO addr23(second word)
00000000nDO #k,addr(second word)
000000010opc—0—aComputed control transfer (to 16-bit Wa)
00000001000—0—aCALL RaPush PC, jump to Wa
00000001001—0—aRCALL RaPush PC, jump to PC+2×Wa
00000001010—0—aGOTO RaJump to Wa
00000001011—0—aBRA RaJump to PC+2×Wa
00000010n<15:1>0CALL addr23Push PC, jump to absolute address
—0——0—n<22:16>
00000011—(Reserved)
00000100n0GOTO addr23Jump to absolute address
—0——0—n<22:16>
000001010BkdRETLW[.B] #k,WdWd = k, pop PC
0000011000—0—RETURNpop PC
0000011001—0—RETFIECZNpop SR, PC
00000111nRCALL addressPush PC, PC += 2×s16
0000100000kDO #k,addrZero-overhead loop: k+1 is repeat count, PC+2×n last instruction
—0—n
0000100000kREPEAT #kRepeat next instruction k+1 times
00001000nRCALL addressPush PC, PC += 2×s16
0000101—(Reserved)
0000110anBRA Oa, addrIf accumulator an overflowed/saturated, PC += 2×simm16
0000111anBRA Sa, addr
0opcodewBqdpsReverse subtract: dest ← source − Ww
00010wBqdpsSUBR[.B] Ww,src,dstCZNdst ← src − Ww = src + ~Ww + 1)
00011wBqdpsSUBBR[.B] Ww,src,dstCZNdst ← src − Ww − C̅ = src + ~Ww + C
0010kdMOV #k,WdWd ← #imm16
0011condnConditional branch to PC+2×n
00110000nBRA OV,addr...if PSR.V is set
00110001nBRA C,addr...if PSR.C is set
00110010nBRA Z,addr...if PSR.Z is set
00110011nBRA N,addr...if PSR.N is set
00110100nBRA LE,addr...if PSR.Z, or PSR.N ≠ PSR.V
00110101nBRA LT,addr...if PSR.N ≠ PSR.V
00110110nBRA LEU,addr...if PSR.Z is set, or PSR.C is clear
00110111nBRA addr...unconditionally
00111000nBRA NOV,addr...if PSR.V is clear
00111001nBRA NC,addr...if PSR.C is clear
00111010nBRA NZ,addr...if PSR.Z is clear
00111011nBRA NN,addr...if PSR.N is clear
00111100nBRA GT,addr...if PSR.Z is clear, and PSR.N = PSR.V
00111101nBRA GE,addr...if PSR.N = PSR.V
00111110nBRA GTU,addr...if PSR.Z is clear, and PSR.C is set
00111111n(Reserved)
0opcodewBqdpsALU operations: dest ← OP(Ww,source)
01000wBqdpsADD[.B] Ww,src,dstCZNdst ← Ww + src
01001wBqdpsADDC[.B] Ww,src,dstCZNdst ← Ww + src + C
01010wBqdpsSUB[.B] Ww,src,dstCZNdst ← Ww − src
01011wBqdpsSUBB[.B] Ww,src,dstCZNdst ← Ww − ~src − C̅ = Ww + ~src + C
01100wBqdpsAND[.B] Ww,src,dstZNdst ← Ww & src
01101wBqdpsXOR[.B] Ww,src,dstZNdst ← Ww ^ src
01110wBqdpsIOR[.B] Ww,src,dstZNdst ← Ww | src
01111wBqdpsMOV[.B] src,dstZNdst ← src (offset mode allowed)
10000fdMOV f,WdWd ← f
10001fsMOV Ws,ff ← Ws
10010kBkdksMOV[.B] [Ws+s10],WdLoad with 10-bit offset
10011kBkdksMOV[.B] Ws,[Wd+s10]Store with 10-bit offset
10100opcodebZB—0—psBit operations on source
10100000b0B—0—psBSET[.B] #b,srcSet bit b of src
10100001b0B—0—psBCLR[.B] #b,srcClear bit b of src
10100010b0B—0—psBTG[.B] #b,srcToggle bit b of src
10100011b00—0—psBTST.C #b,srcCSet PSR.C = bit b of src
10100011b10—0—psBTST.Z #b,srcZSet PSR.Z = bit b of src
10100100bZ0—0—psBTSTS.z #b,srcC/ZTest bit b of src (into C or Z), then set
10100101Zw0—0—psBTST.z Ww,srcC/ZTest bit Ww of src
10100110b00—0—psBTSS #b,srcTest bit, skip if set
10100111b00—0—psBTS #b,srcTest bit, skip if clear
10101opcodebfBit operations on f
10101000bfbBSET[.B] f,#bSet bit b of f
10101001bfBCLR.B f,#bClear bit b of f
10101010bfBTG.B f,#bToggle bit b of f
10101011bfBTST.B f,#bZTest bit b of f
10101100bfBTSTS.B f,#bZTest bit b of f, then set
10101101Zw0—0—psBSW.zsrc,WwCopy PSW.C or PSW.Z to bit Ww of src
10101110bfBTSS f,#bTest bit, skip if set
10101111bfBTSC f,#bTest bit, skip if clear
101100opcodeBkdRegister-immediate operations: Wd ← OP(Wd,k)
101100000BkdADD[.B] #u10,WdCZNWd ← Wd + k
101100001BkdADC[.B] #u10,WdCZNWd ← Wd + k + C
101100010BkdSUB[.B] #u10,WdCZNWd ← Wd − k
101100011BkdSUBB[.B] #u10,WdCZNWd ← Wd − k − C̅
101100100BkdAND[.B] #u10,WdZNWd ← Wd & k
101100101BkdXOR[.B] #u10,WdZNWd ← Wd ^ k
101100110BkdIOR[.B] #u10,WdZNWd ← Wd | k
101100111BkdMOV[.B] #u10,WdWd ← k
101101opcodeBDfALU operations: dest ← OP(f,W0)
101101000BDfADD[.B] f[,WREG]CZNdest ← f + W0
101101001BDfADC[.B] f[,WREG]CZNdest ← f + W0 + C
101101010BDfSUB[.B] f[,WREG]CZNdest ← f − W0
101101011BDfSUBB[.B] f[,WREG]CZNdest ← f − W0 + C̅
101101100BDfAND[.B] f[,WREG]ZNdest ← f & W0
101101101BDfXOR[.B] f[,WREG]ZNdest ← f ^ W0
101101110BDfIOR[.B] f[,WREG]ZNdest ← f | W0
101101111B1fMOV[.B] WREG,ff ← W0
1011100opcwd0ps16×16→32 multiplication
101110000wd0psMUL.UU Ww,src,WdWd+1:Wd ← Ww × src (unsigned)
101110001wd0psMUL.US Ww,src,WdWd+1:Wd ← Ww × src (src signed)
101110010wd0psMUL.SU Ww,src,WdWd+1:Wd ← Ww × src (Ww signed)
101110011wd0psMUL.SS Ww,src,WdWd+1:Wd ← Ww × src (signed)
1011101opcBqdpsProgram memory access (indirect modes only)
101110100BqdpsTBLRDL[.B] src,dstdst ← ROM[TBLPAG:src] (bits 15:0)
101110101BqdpsTBLRDH[.B] src,dstdst ← ROM[TBLPAG:src] (bits 23:16)
101110110BqdpsTBLWTL[.B] src,dstROM[TBLPAG:dst] ← src (bits 15:0)
101110111BqdpsTBLWTH[.B] src,dstROM[TBLPAG:dst] ← src (bits 23:16)
101111000B0fMUL[.B] fW3:W2 ← f × W0 (unsigned)
101111000B1—(Reserved)
101111001—(Reserved)
10111101—(Reserved)
1011111000—0—d0psMOV.D src,WdLoad register pair
1011111010qd—0—s0MOV.D Ws,dstStore register pair
10111111—(Reserved)
11000mASxyijaDSP MAC (dsPIC only)
11001Other DSP instructions (dsPIC only)
1100111100—0—dpsFF1R src,WdCFind first one from right (lsb)
1100111110—0—dpsFF1L src,WdCFind first one from left (msb)
110100opcodeBqdpsShift/rotate general operand
110100000BqdpsSL[.B] src,dstCZNdst ← src << 1, shift left (into carry)
110100010BqdpsLSR[.B] src,dstCZNdst ← src >> 1, logical shift right
110100011BqdpsASR[.B] src,dstCZNdst ← src >> 1, arithmetic shift right
110100100BqdpsRLNC[.B] src,dstZNdst ← src <<< 1, rotate left (no carry)
110100101BqdpsRLC[.B] src,dstCZNC:dst ← src:C << 1, rotate left through carry
110100110BqdpsRRNC[.B] src,dstZNdst ← src >>> 1, rotate right (no carry)
110100111BqdpsRRC[.B] src,dstCZNdst:C ← C:src >> 1, rotate right through carry
110101opcodeBDfShift/rotate f
110101000BDfSL[.B] f[,WREG]CZNdest ← f << 1, shift left (into carry)
110101010BDfLSR[.B] f[,WREG]CZNdest ← f >> 1, logical shift right
110101011BDfASR[.B] f[,WREG]CZNdest ← f >> 1, arithmetic shift right
110101100BDfRLNC[.B] f[,WREG]ZNdest ← f <<< 1, rotate left (no carry)
110101101BDfRLC[.B] f[,WREG]CZNC:dest ← f:C << 1, rotate left through carry
110101110BDfRRNC[.B] f[,WREG]ZNdest ← f >>> 1, rotate right (no carry)
110101111BDfRRC[.B] f[,WREG]CZNdest:C ← C:f >> 1, rotate right through carry
11011000UtdD00sDivide step (prefix with REPEAT #17)
110110000—0—d000sDIV.S Wd,WsCZNW0 ← Wd/Ws, W1 ← remainder
110110000td100sDIV.SD Wd,WsCZNW0 ← Wt:Wd/Ws, W1 ← remainder
110110001—0—d000sDIV.U Wd,WsCZNW0 ← Wd/Ws, W1 ← remainder
110110001td100sDIV.UD Wd,WsCZNW0 ← Wt:Wd/Ws, W1 ← remainder
110110010t—0—000sDIVF Wt,WsCZNW0 ← Wt:0/Ws, W1 ← remainder
110110011—(Reserved)
1101101—(Reserved)
110111opcodewdi00sShift/rotate multiple
110111000wd000sSL Ww,Ws,WdZNWd ← Ww << Ws
110111000wd100kSL Wv,#u4,WdZNWd ← Ww << k
110111100wd000sLSR Ww,Ws,WdZNWd ← Ww >> Ws, logical shift right
110111100wd100kLSR Wv,#u4,WdZNWd ← Ww >> k, logical shift right
110111101wd000sASR Ww,Ws,WdZNWd ← Ww >> Ws, arithmetic shift right
110111101wd100kASR Wv,#u4,WdZNWd ← Ww >> k, arithmetic shift right
110111110—0—dpsFBCL src,WdCFind permissible arithmetic normalization shift
111000000—0—B000psCP0[.B] srcCZNCompare with zero, src − 0
111000010wB000psCP[.B] Ww,srcCZNCompare, Ww − src (Ww + ~src + 1)
111000011wB000psCPB[.B] Ww,srcCZNCompare with borrow, Ww − src − C̅ (Ww + ~src + C)
111000100B0fCP0[.B] fCZNCompare with zero, f − 0
111000110B0fCP[.B] fCZNCompare, f − W0
111000111B0fCPB[.B] fCZNCompare with borrow, f − W0 − C̅ (f + ~W0 + C)
1110010—(Reserved)
1110011opcwB—0—sCompare and skip
111001100wB—0—sCPSGT[.B] Ww,Ws...if Ww > Ws, signed
111001101wB—0—sCPSLT[.B] Ww,Ws...if Ww < Ws, signed
111001110wB—0—sCPSNE[.B] Ww,Ws...if Ww ≠ Ws
111001111wB—0—sCPSNE[.B] Ww,Ws...if Ww = Ws
111010000BqdpsINC[.B] src,dstCZNdst ← src+1
111010001BqdpsINC2[.B] src,dstCZNdst ← src+2
111010010BqdpsDEC[.B] src,dstCZNdst ← src−1
111010011BqdpsDEC2[.B] src,dstCZNdst ← src−2
111010100BqdpsNEG[.B] src,dstCZNdst ← ~src+1
111010101BqdpsCOM[.B] src,dstZNdst ← ~src
111010110Bqd—0—CLR[.B] dstdst ← 0
111010111Bqd—0—SETM[.B] dstdst ← ~0
111011000BDfINC[.B] f[,WREG]CZNdest ← f+1
111011001BDfINC2[.B] f[,WREG]CZNdest ← f+2
111011010BDfDEC[.B] f[,WREG]CZNdest ← f−1
111011011BDfDEC[.B] f[,WREG]CZNdest ← f−2
111011100BDfNEG[.B] f[,WREG]CZNdest ← ~f+1
111011101BDfCOM[.B] f[,WREG]ZNdest ← ~f
111011110BDfCLR[.B] f[,WREG]dest ← 0
111011111BDfSETM[.B] f[,WREG]dest ← ~0
111100mA1xyijopcDSP MPY/MAC/ED/EDAC (dsPIC only)
111101—(Reserved)
11111000f0PUSH fPush f on top of stack
11111001f0POP fPop f from top of stack
1111101000kLNK #u14Push W14, W14 ← W15, W15 += k
1111101010—0—ULNKW15 ← W14, pop W14
1111101100000dpsSE src,dstCZNdst ← sign_extend(src), copy bit 7 to bits 15:8
1111101110000dpsZE src,dst1Z0dst ← zero_extend(src), clear bits 15:8
1111110000kDISI #u14Disable interrupt for k+1 cycles
1111110100000d000sEXCH Ws,WdSwap contents of registers Ws, Wd
11111101010000000000sDAW.B WsCDecimal adjust based on C, DC
111111011B0000000000sSWAP[.B] WsSwap halves of Ws
1111111000—0—RESETSoftware reset
11111110010—0—kPWRSAV #u1Go into sleep or idle mode
11111110011—0—CLRWDTClear watchdog timer
11111110100—0—POP.SPop shadow registers (W0–3, part of PSR)
11111110101—0—PUSH.SPush shadow registers (W0–3, part of PSR)
1111111011—(Reserved)
11111111—NOPRNo operation (version #2)

Related Research Articles

<span class="mw-page-title-main">Accumulator (computing)</span> Register in which intermediate arithmetic and logic results of a CPU are stored

In a computer's central processing unit (CPU), the accumulator is a register in which intermediate arithmetic logic unit results are stored.

<span class="mw-page-title-main">Data General Nova</span> 16-bit minicomputer series

The Data General Nova is a series of 16-bit minicomputers released by the American company Data General. The Nova family was very popular in the 1970s and ultimately sold tens of thousands of units.

<span class="mw-page-title-main">Motorola 68HC11</span> 8-bit microcontroller family

The 68HC11 is an 8-bit microcontroller family introduced by Motorola Semiconductor in 1984. It descended from the Motorola 6800 microprocessor by way of the 6801. The 68HC11 devices are more powerful and more expensive than the 68HC08 microcontrollers and are used in automotive applications, barcode readers, hotel card key writers, amateur robotics, and various other embedded systems. The MC68HC11A8 was the first microcontroller to include CMOS EEPROM.

<span class="mw-page-title-main">Zilog Z80</span> 8-bit microprocessor

The Zilog Z80 is an 8-bit microprocessor designed by Zilog that played an important role in the evolution of early computing. Software-compatible with the Intel 8080, it offered a compelling alternative due to its better integration and increased performance. The Z80 boasted fourteen registers compared to the 8080's seven, along with additional instructions for bit manipulation, making it a more powerful chip.

In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, such as a central processing unit (CPU), is called an implementation of that ISA.

<span class="mw-page-title-main">MCS-51</span> Single chip microcontroller series by Intel

The Intel MCS-51 is a single chip microcontroller (MCU) series developed by Intel in 1980 for use in embedded systems. The architect of the Intel MCS-51 instruction set was John H. Wharton. Intel's original versions were popular in the 1980s and early 1990s, and enhanced binary compatible derivatives remain popular today. It is a complex instruction set computer, but also has some of the features of RISC architectures, such as a large register set and register windows, and has separate memory spaces for program instructions and data.

<span class="mw-page-title-main">Intel 8085</span> 8-bit microprocessor by Intel

The Intel 8085 ("eighty-eighty-five") is an 8-bit microprocessor produced by Intel and introduced in March 1976. It is the last 8-bit microprocessor developed by Intel.

<span class="mw-page-title-main">PIC microcontrollers</span> Line of single-chip microprocessors from Microchip Technology

PIC is a family of microcontrollers made by Microchip Technology, derived from the PIC1640 originally developed by General Instrument's Microelectronics Division. The name PIC initially referred to Peripheral Interface Controller, and is currently expanded as Programmable Intelligent Computer. The first parts of the family were available in 1976; by 2013 the company had shipped more than twelve billion individual parts, used in a wide variety of embedded systems.

Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions in that architecture identify the operand(s) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

The National Semiconductor COP8 is an 8-bit CISC core microcontroller. COP8 is an enhancement to the earlier COP400 4-bit microcontroller family. COP8 main features are:

The TMS9900 was one of the first commercially available, single-chip 16-bit microprocessors. Introduced in June 1976, it implemented Texas Instruments' TI-990 minicomputer architecture in a single-chip format, and was initially used for low-end models of that lineup.

<span class="mw-page-title-main">Fairchild F8</span> 8-bit microprocessor first shipped in 1975

The Fairchild F8 is an 8-bit microprocessor system from Fairchild Semiconductor, announced in 1974 and shipped in 1975. The original processor family included four main 40-pin integrated circuits (ICs); the 3850 CPU which was the arithmetic logic unit, the 3851 Program Storage Unit (PSU) which contained 1 KB of program ROM and handled instruction decoding, and the optional 3852 Dynamic Memory Interface (DMI) or 3853 Static Memory Interface (SMI) to control additional RAM or ROM holding the user programs or data. The 3854 DMA was another optional system that added direct memory access into the RAM controlled by the 3852.

The Atmel AVR instruction set is the machine language for the Atmel AVR, a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage.

<span class="mw-page-title-main">TI-990</span> Series of 16-bit computers by Texas Instruments.

The TI-990 was a series of 16-bit minicomputers sold by Texas Instruments (TI) in the 1970s and 1980s. The TI-990 was a replacement for TI's earlier minicomputer systems, the TI-960 and the TI-980. It had several unique features, and was easier to program than its predecessors.

TLCS is a prefix applied to microcontrollers made by Toshiba. The product line includes multiple families of CISC and RISC architectures. Individual components generally have a part number beginning with "TMP". E.g. the TMP8048AP is a member of the TLCS-48 family.

The Mitsubishi 740, also known as MELPS 740, is a series of 8-bit CMOS microcontrollers and microprocessors with an enhanced MOS Technology 6502 compatible core based on the expanded WDC 65C02. The ICs were manufactured by Mitsubishi Electric during the 1980s and 1990s.

<span class="mw-page-title-main">ST6 and ST7</span> 8-bit microcontroller product lines from STMicroelectronics

The ST6 and ST7 are 8-bit microcontroller product lines from STMicroelectronics. They are commonly used in small embedded applications like washing machines.

<span class="mw-page-title-main">WDC 65C816</span> 8/16-bit microprocessor

The W65C816S is a 16-bit microprocessor (MPU) developed and sold by the Western Design Center (WDC). Introduced in 1983, the W65C816S is an enhanced version of the WDC 65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU. The 65C816 is the CPU for the Apple IIGS and, in modified form, the Super Nintendo Entertainment System.

<span class="mw-page-title-main">STM8</span>

The STM8 is an 8-bit microcontroller family by STMicroelectronics. The STM8 microcontrollers use an extended variant of the ST7 microcontroller architecture. STM8 microcontrollers are particularly low cost for a full-featured 8-bit microcontroller.

The Mostek MK5065 was an 8-bit microprocessor introduced by Mostek in early 1974. The design was originally developed by Motorola for use in an Olivetti electronic calculator, and was licensed to Mostek for use in non-calculator roles. It featured three sets of processor registers, allowing it to switch to an interrupt handler in a single cycle, and a wait-for-data mode that aided direct memory access.

References

  1. ↑ Gruppuso, Frank M. (1982). "Chapter 35 PIC1650: Chip Architecture and Operation" (PDF). In Siewiorek, Daniel P.; Bell, C. Gordon; Newell, Allen (eds.). Computer Structures: Principles and Examples (PDF). McGraw-Hill. ISBN   0-07-057302-6 . Retrieved 2024-08-18.
  2. ↑ PIC10F200/202/204/206 Data Sheet (PDF). Microchip Technology. 2007. p. 52. Archived from the original (PDF) on 2015-08-11. Retrieved 2015-01-15.
  3. ↑ General Instrument. PIC1670 8-bit Microcomputer (PDF) (Data Sheet). Retrieved 2024-08-18.
  4. ↑ "義隆電子股份有限公司義隆電子，再創未來！".
  5. ↑ ELAN Microelectronics Corp. (26 April 2016), EM78P157N 8-bit microcontroller with OTP ROM Product Specification (PDF), version 1.3, archived (PDF) from the original on 2016-03-04, retrieved 2020-06-06
  6. 1 2 ELAN Microelectronics Corp. (25 April 2016), EM78P143 8-bit microprocessor with OTP ROM Product Specification (PDF), version 1.7, p. 77, retrieved 2020-06-06
  7. ↑ ELAN Microelectronics Corp. (April 2016), EM78P346N 8-bit microprocessor with OTP ROM Product Specification (PDF), version 1.5, p. 77, retrieved 2019-07-11
  8. ↑ ELAN Microelectronics Corp. (17 April 2000), EM78860 8-bit Micro-controller (PDF), p. 17, retrieved 2019-07-11
  9. ↑ ELAN Microelectronics Corp. (15 March 2013), EM78F648/644/642/641N/548/544/542/541N Flash Series 8-Bit Microcontroller Product Specification (PDF), version 1.2, pp. 162–165, retrieved 2019-07-11
  10. ↑ Derived from instruction encoding tables in Elan eUIDE II v2.19.60.14, released 2019-05-01, accessed 2019-07-13. Specifically the Bin/*.cfg files.
  11. ↑ ELAN Microelectronics Corp. (2014-01-14), EM78XXX 15-Bit Instruction Set (PDF), retrieved 2019-07-13
  12. ↑ "Introducing the Enhanced Mid-Range Architecture" (PDF). Microchip.
  13. 1 2 Holtek Semiconductor Inc. (11 December 2016), HT8 MCU Extended Instruction Set Applications (PDF) (Application Note), AN0407E, retrieved 2024-02-09
  14. ↑ Holtek Semiconductor Inc. (26 November 2019), 2.4GHz 8-Bit Flash RF TX/RX MCU BC66F840/BC66F850/BC66F860 (PDF) (Data sheet), version 1.60, p. 32, retrieved 2024-02-09. Note that operand addresses only go to 0xFF, with additional RAM addressed by banking.
  15. ↑ Wolf, Ash "Ninji" (12 December 2018). "Mouse Adventures #3: Writing a Disassembler" . Retrieved 8 July 2019.
  16. ↑ Carlson, Jay (6 September 2019). "What's up with these 3-cent microcontrollers? (A review of the Padauk PMS150C and friends)" . Retrieved 2020-05-18.
  17. 1 2 "The "terrible" 3 cent MCU – a short survey of sub $0.10 microcontrollers". Tim's blog. 12 August 2019. Retrieved 2020-05-18.
  18. ↑ "Free PDK Documentation". Padauk µCs sport an interesting architecture that can be a seen as a ... extension of the Microchip PIC architecture.
  19. ↑ "Chiptunes on an ATtiny4 and the 3 Cent Micro: Porting to Padauk". According to some, Padauk's instruction set is heavily inspired by older PICs, with most operations taking place on a single accumulator register.
  20. ↑ Jenny List "Everything you want to know about the cheapest processors available". 2019.
  21. ↑ Wolf, Ash "Ninji" (12 December 2018). "Documentation for PADAUK FPPA MCUs". GitHub . Retrieved 2020-05-18.
  22. ↑ Padauk Technology Co. Ltd. (11 December 2018). "PMC150/PMS150 8-bit OTP Type IO Controller" (PDF) (data sheet). Version 1.8. pp. 38–51. PDK-DS-PMX150-EN-V108. Retrieved 2020-06-08.
  23. ↑ Wolf, Ash "Ninji" (23 May 2020). "PADAUK FPPA core devices (14 bit) instruction set" . Retrieved 2020-06-08.
  24. ↑ Padauk Technology Co. Ltd. (18 June 2019). "PFS154 8bit MTP Type IO controller Data Sheet" (PDF). Version 1.04. pp. 71–84. PDK-DS-PFS154_RN_V104. Retrieved 2020-06-09.
  25. ↑ "Microchip PIC micros and C - source and sample code".
  26. ↑ Microchip Technology, Inc. (2007), PIC18F1220/1320 Data Sheet (PDF), retrieved 2012-04-02
  27. ↑ "Microchip Technology debuts world's highest performing 16-bit microcontrollers: dsPIC". Archived from the original on 2004-12-13.
  28. ↑ dsPIC30F Programmer's Reference Manual (PDF), Microchip Technology, 2008, DS70157C, retrieved 2012-07-02
This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.