Pad cratering is a mechanically induced fracture in the resin between copper foil and outermost layer of fiberglass of a printed circuit board (PCB). It may be within the resin or at the resin to fiberglass interface.
The pad remains connected to the component (usually a Ball Grid Array, BGA) and leaves a "crater" on the surface of the printed circuit board.
Pad cratering most often occurs during dynamic mechanical events such as mechanical shock or board flexure due to In-circuit test (ICT), board depaneling, or connector insertion. [1] However, pad cratering has also been known to occur during thermal shock or even thermal cycling. Susceptibility to pad cratering can be impacted by several factors such as: PCB thickness, PCB laminate material properties, component size and stiffness, component location, and solder alloy selection among other factors. [2] [3] [4]
IPC-9708 provides three test methods to characterize the pad cratering of a component and PCBA: pin pull, ball pull, and ball shear testing. [5] In the pin pull test a pin is soldered to pads and pulled until fracture. It is a useful test for all pad geometries and is sensitive to board design and materials. The ball pull test is specifically design for BGA components and has a large sensitivity to the solder alloy and joint formation. The ball shear test is also specified for BGA components and involves shearing the solder balls of the BGA. This test is typically the most convenient but is less sensitive to the design and material as compared to the ball pull test. [6] Although IPC-9708 specifies procedures for each test type, the challenge is that no standard pass/fail criteria are defined. This is viewed as application-specific and must be defined by the user based on their design, environment, and reliability requirements.
Another applicable test method is IPC/JEDEC-9702, which is a monotonic bend test method used to characterize board level interconnects. [7] This can be relevant for pad cratering resulting from board flexure, however this test method is broader and does not specifically focus on pad cratering failure modes.
Board level reliability testing is a common approach to assessing product reliability. Performing temperature cycling, mechanical drop/shock, and vibration testing is a good way to evaluate pad cratering. However, similar to IPC/JEDEC-9702, this can be cost and time intensive and does not specifically focus on pad cratering failure modes. [8]
Pad cratering can be difficult to detect during functional testing. This is especially the case with small or partial cracking that can escape testing and cause latent field failures. [9] Even if a component failure is identified, diagnosing the failure mode as pad cratering can be difficult. Conventional nondestructive testing and failure analysis techniques such as visual inspection and X-Ray microscopy may not detect the issue. Electrical characterization is an example of a nondestructive technique that can be useful, however this may not detect an anomaly if there is only partial cracking.
Typically, pad cratering is detected or confirmed via destructive testing and failure analysis such as dye and pry, acoustic emissions, [10] cross sectioning, and Scanning Electron Microscopy.
There are several mitigation techniques that can used to reduce the risk of pad cratering. The appropriate method(s) is often driven by design and resource constraints.
Limiting Board Flexure: If cratering is due to mechanical overstress then limiting board flexure is typically the best mitigation technique. [1] [9] [4]
Simulation: Modeling and simulation can help proactively avoid pad cratering failures. [1] [6] Relevant examples include ICT failures or products with potential for large shock events (i.e. portable electronics). Finite Element Analysis can be done using a physics of failure approach to determine risk of overstress and pad cratering. This proactive approach can rapidly evaluate multiple designs early on, potentially avoiding expensive design changes or warranty costs later on.
Underfill, Edge Bonding, and Corner Staking: Epoxies and underfill materials can be added to provide mechanical support and reduce board and solder strain during flexing. This is more common in cases where the component selection and PCBA design are fixed. There are differences between each technique which makes proper understanding of the environment and application important. [4]
Solder Alloy: Solder alloy selection can impact susceptibility to pad cratering. Typically, pad cratering is considered a high strain rate event with minimal creep, however there is still potential for plasticity in the solder. More compliant solders or those with lower yield points will reduce pad cratering potential by providing additional load sharing.
Board Thickness and Laminate Material: Board thickness and laminate material properties such as Young's modulus and Coefficient of Thermal Expansion (CTE) will impact susceptibility to pad cratering.
Board Redesign: If pad cratering persists then a redesign may be required. This could include changing component location or adjusting between solder mask defined (SMD) and non-solder mask defined (NSMD) pads.
Additional information on pad cratering in printed circuit boards can be found in the following links:
A printed circuit board is a medium used to connect electronic components to one another in a controlled manner. It takes the form of a laminated sandwich structure of conductive and insulating layers: each of the conductive layers is designed with an artwork pattern of traces, planes and other features etched from one or more sheet layers of copper laminated onto and/or between sheet layers of a non-conductive substrate. Electrical components may be fixed to conductive pads on the outer layers in the shape designed to accept the component's terminals, generally by means of soldering, to both electrically connect and mechanically fasten them to it. Another manufacturing process adds vias: plated-through holes that allow interconnections between layers.
Wire bonding is the method of making interconnections between an integrated circuit (IC) or other semiconductor device and its packaging during semiconductor device fabrication. Although less common, wire bonding can be used to connect an IC to other electronics or to connect from one printed circuit board (PCB) to another. Wire bonding is generally considered the most cost-effective and flexible interconnect technology and is used to assemble the vast majority of semiconductor packages. Wire bonding can be used at frequencies above 100 GHz.
A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.
Surface-mount technology (SMT), originally called planar mounting, is a method in which the electrical components are mounted directly onto the surface of a printed circuit board (PCB). An electrical component mounted in this manner is referred to as a surface-mount device (SMD). In industry, this approach has largely replaced the through-hole technology construction method of fitting components, in large part because SMT allows for increased manufacturing automation which reduces cost and improves quality. It also allows for more components to fit on a given area of substrate. Both technologies can be used on the same board, with the through-hole technology often used for components not suitable for surface mounting such as large transformers and heat-sinked power semiconductors.
Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting dies such as semiconductor devices, IC chips, integrated passive devices and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric's Light Military Electronics Department, Utica, New York. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry, it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and fine wires are welded onto the chip pads and lead frame contacts to interconnect the chip pads to external circuitry.
A quad flat package (QFP) is a surface-mounted integrated circuit package with "gull wing" leads extending from each of the four sides. Socketing such packages is rare and through-hole mounting is not possible. Versions ranging from 32 to 304 pins with a pitch ranging from 0.4 to 1.0 mm are common. Other special variants include low-profile QFP (LQFP) and thin QFP (TQFP).
Reflow soldering is a process in which a solder paste is used to temporarily attach one or thousands of tiny electrical components to their contact pads, after which the entire assembly is subjected to controlled heat. The solder paste reflows in a molten state, creating permanent solder joints. Heating may be accomplished by passing the assembly through a reflow oven, under an infrared lamp, or (unconventionally) by soldering individual joints with a desoldering hot air pencil.
Rework is the term for the refinishing operation or repair of an electronic printed circuit board (PCB) assembly, usually involving desoldering and re-soldering of surface-mounted electronic components (SMD). Mass processing techniques are not applicable to single device repair or replacement, and specialized manual techniques by expert personnel using appropriate equipment are required to replace defective components; area array packages such as ball grid array (BGA) devices particularly require expertise and appropriate tools. A hot air gun or hot air station is used to heat devices and melt solder, and specialised tools are used to pick up and position often tiny components.
A bed of nails tester is a traditional electronic test fixture used for in-circuit testing. It has numerous pins inserted into holes in an epoxy phenolic glass cloth laminated sheet (G-10) which are aligned using tooling pins to make contact with test points on a printed circuit board and are also connected to a measuring unit by wires. Named by analogy with a real-world bed of nails, these devices contain an array of small, spring-loaded pogo pins; each pogo pin makes contact with one node in the circuitry of the DUT. By pressing the DUT down against the bed of nails, reliable contact can be quickly and simultaneously made with hundreds or even thousands of individual test points within the circuitry of the DUT. The hold-down force may be provided manually or by means of a vacuum or a mechanical presser, thus pulling the DUT downwards onto the nails.
Solder paste is used in the manufacture of printed circuit boards to connect surface mount components to pads on the board. It is also possible to solder through-hole pin in paste components by printing solder paste in and over the holes. The sticky paste temporarily holds components in place; the board is then heated, melting the paste and forming a mechanical bond as well as an electrical connection. The paste is applied to the board by jet printing, stencil printing or syringe; then the components are put in place by a pick-and-place machine or by hand.
Flat no-leads packages such as quad-flat no-leads (QFN) and dual-flat no-leads (DFN) physically and electrically connect integrated circuits to printed circuit boards. Flat no-leads, also known as micro leadframe (MLF) and SON, is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. Flat no-lead is a near chip scale plastic encapsulated package made with a planar copper lead frame substrate. Perimeter lands on the package bottom provide electrical connections to the PCB. Flat no-lead packages usually, but not always, include an exposed thermally conductive pad to improve heat transfer out of the IC. Heat transfer can be further facilitated by metal vias in the thermal pad. The QFN package is similar to the quad-flat package (QFP), and a ball grid array (BGA).
Automated optical inspection (AOI) is an automated visual inspection of printed circuit board (PCB) manufacture where a camera autonomously scans the device under test for both catastrophic failure and quality defects. It is commonly used in the manufacturing process because it is a non-contact test method. It is implemented at many stages through the manufacturing process including bare board inspection, solder paste inspection (SPI), pre-reflow and post-re-flow as well as other stages.
Package on a package (PoP) is an integrated circuit packaging method to vertically combine discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones, personal digital assistants (PDA), and digital cameras, at the cost of slightly higher height requirements. Stacks with more than 2 packages are uncommon, due to heat dissipation considerations.
Microvias are used as the interconnects between layers in high density interconnect (HDI) substrates and printed circuit boards (PCBs) to accommodate the high input/output (I/O) density of advanced packages. Driven by portability and wireless communications, the electronics industry strives to produce affordable, light, and reliable products with increased functionality. At the electronic component level, this translates to components with increased I/Os with smaller footprint areas, and on the printed circuit board and package substrate level, to the use of high density interconnects (HDIs).
Sherlock Automated Design Analysis is a software tool developed by DfR Solutions for analyzing, grading, and certifying the expected reliability of products at the circuit card assembly level. Based on the science of Physics of Failure, Sherlock predicts failure mechanism-specific failure rates over time using a combination of finite element method and material properties to capture stress values and first order analytical equations to evaluate damage evolution. The software is designed for use by design and reliability engineers and managers in the electronics industry. DfR Solutions is based in Beltsville, Maryland, USA, and was acquired by ANSYS, Inc. in May 2019.
In integrated circuit packaging, a solder ball, also a solder bump is a ball of solder that provides the contact between the chip package and the printed circuit board, as well as between stacked packages in multichip modules; in the latter case, they may be referred to as microbumps, since they are usually significantly smaller than the former. The solder balls can be placed manually or by automated equipment, and are held in place with a tacky flux.
Solder fatigue is the mechanical degradation of solder due to deformation under cyclic loading. This can often occur at stress levels below the yield stress of solder as a result of repeated temperature fluctuations, mechanical vibrations, or mechanical loads. Techniques to evaluate solder fatigue behavior include finite element analysis and semi-analytical closed-form equations.
Digital image correlation analyses have applications in material property characterization, displacement measurement, and strain mapping. As such, DIC is becoming an increasingly popular tool when evaluating the thermo-mechanical behavior of electronic components and systems.
Dye-n-Pry, also called Dye And Pry, Dye and Pull, Dye Staining, or Dye Penetrant, is a destructive analysis technique used on surface mount technology (SMT) components to either perform failure analysis or inspect for solder joint integrity. It is an application of dye penetrant inspection.