RF Micropower

Last updated
RF Micropower
Type Private
Industry Semiconductors
FoundedJuly 18, 2000 (2000-07-18)
FounderDr. Trevor Thornton
Headquarters
Phoenix, Arizona
,
United States
ProductsSi-MESFETs, Discrete Power transistors, RF power amplifiers, Low-dropout regulators, PLLs for Medical Implant Communication Service Band
Website rfmicropower.com

RF Micropower is a fabless semiconductor company based in Phoenix, Arizona that sells and licenses the RFuP [1] technology that was initially developed by SJT Micropower, Inc. The company's proprietary technology enables high voltage Si-MESFET transistors to be fabricated on commercial SOI CMOS processes without altering the native process or adding additional fabrication steps [2] which allows high levels of monolithic integration. These power transistors can operate at voltages that are 20 times higher than the baseline CMOS transistors [3] and at several Watts of power. The technology has been implemented in various integrated circuit solutions including RF power amplifiers and power regulation circuits. According to their website, [4] they have demonstrated Si-MESFETs at the 350 nm, 250 nm, 150 nm, 45 nm and 32 nm process nodes. The smallest process node for MESFETs on any type of substrate is currently 32 nm. [5]

Contents

Acceptance of Si-MESFETs

Applications of RF Micropower's Si-MESFET (metal-semiconductor field-effect-transistor) technology in linear and switching regulators for radiation environments has been reported by the NASA Goddard Space Flight Center and was featured in the September 2011 [6] and February 2013 [7] Issues of NASA Tech Briefs. In Chapter 6 of the book Extreme Environment Electronics (edited by John D. Cressler and H. Alan Mantooth), [8] Johnathan A. Pellish from NASA and Lewis M. Cohn from the Naval Research Laboratory state that MESFETs on SOI substrates are suitable for applications from -180 °C and 250 °C and have been demonstrated to operate through 5 Mrad of total ionizing dose. The Si-MESFETs and their corresponding applications were also featured prominently in Chapters 23 and 63 of the book. [9] Most recently, results from the 45 nm process node were published in the book Frontiers in Electronics (edited by Sorin Cristoloveanu and Michael S. Shur). [10]

Origins

SJT Micropower, Inc was founded in 2000 by Dr. Trevor Thornton [11] who has multiple patents in the field of MESFET fabrication and design. In 2013, SJT Micropower, Inc started doing business as RF Micropower. Dr. Thornton continues to serve as the company's president and is concurrently a professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. [12] Dr. Seth J. Wilk currently serves as the CEO. [13]

From 2006 to 2012, the company was awarded a total of $2,782,727 through SBIR/STTR grants [14] and as of 2012 has been published in 24 different peer-reviewed conference and journal proceedings. [15]

Locations

RF Micropower is headquartered in Phoenix, Arizona and has sales offices in Austin, Texas and Morristown, New Jersey.

Related Research Articles

<span class="mw-page-title-main">Integrated circuit</span> Electronic circuit formed on a small, flat piece of semiconductor material

An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material, usually silicon. Large numbers of miniaturized transistors and other electronic components are integrated together on the chip. This results in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete components, allowing a large transistor count. The IC's mass production capability, reliability, and building-block approach to integrated circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in virtually all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones and other home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs such as modern computer processors and microcontrollers.

<span class="mw-page-title-main">MOSFET</span> Type of field-effect transistor

The metal–oxide–semiconductor field-effect transistor is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. A metal-insulator-semiconductor field-effect transistor (MISFET) is a term almost synonymous with MOSFET. Another synonym is IGFET for insulated-gate field-effect transistor.

<span class="mw-page-title-main">CMOS</span> Technology for constructing integrated circuits

Complementary metal–oxide–semiconductor is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.

Bipolar CMOS (BiCMOS) is a semiconductor technology that integrates two semiconductor technologies, those of the bipolar junction transistor and the CMOS logic gate, into a single integrated circuit. In more recent times the bipolar processes have been extended to include high mobility devices using silicon–germanium junctions.

Silicon on sapphire (SOS) is a hetero-epitaxial process for metal–oxide–semiconductor (MOS) integrated circuit (IC) manufacturing that consists of a thin layer (typically thinner than 0.6 µm) of silicon grown on a sapphire (Al2O3) wafer. SOS is part of the silicon-on-insulator (SOI) family of CMOS (complementary MOS) technologies.

In semiconductor manufacturing, silicon on insulator (SOI) technology is fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire. The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.

A MESFET is a field-effect transistor semiconductor device similar to a JFET with a Schottky (metal–semiconductor) junction instead of a p–n junction for a gate.

The 90 nm process is a level of MOSFET (CMOS) fabrication process technology that was commercialized by the 2003–2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology.

<span class="mw-page-title-main">Mixed-signal integrated circuit</span> Integrated circuit

A mixed-signal integrated circuit is any integrated circuit that has both analog circuits and digital circuits on a single semiconductor die. Their usage has grown dramatically with the increased use of cell phones, telecommunications, portable electronics, and automobiles with electronics and digital sensors.

<span class="mw-page-title-main">Fin field-effect transistor</span> Type of non-planar transistor

A fin field-effect transistor (FinFET) is a multigate device, a MOSFET built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double or even multi gate structure. These devices have been given the generic name "FinFETs" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than planar CMOS technology.

The 32 nm node is the step following the 45 nm process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch of a memory cell at this technology level. Toshiba produced commercial 32 GiB NAND flash memory chips with the 32 nm process in 2009. Intel and AMD produced commercial microchips using the 32-nanometre process in the early 2010s. IBM and the Common Platform also developed a 32 nm high-κ metal gate process. Intel began selling its first 32 nm processors using the Westmere architecture on 7 January 2010.

<span class="mw-page-title-main">Shallow trench isolation</span> Integrated circuit

Shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. Older CMOS technologies and non-MOS technologies commonly use isolation based on LOCOS.

SONOS, short for "silicon–oxide–nitride–oxide–silicon", more precisely, "polycrystalline silicon"—"silicon dioxide"—"silicon nitride"—"silicon dioxide"—"silicon", is a cross sectional structure of MOSFET (metal–oxide–semiconductor field-effect transistor), realized by P.C.Y. Chen of Fairchild Camera and Instrument in 1977. This structure is often used for non-volatile memories, such as EEPROM and flash memories. It is sometimes used for TFT LCD displays. It is one of CTF (charge trap flash) variants. It is distinguished from traditional non-volatile memory structures by the use of silicon nitride (Si3N4 or Si9N10) instead of "polysilicon-based FG (floating-gate)" for the charge storage material. A further variant is "SHINOS" ("silicon"—"hi-k"—"nitride"—"oxide"—"silicon"), which is substituted top oxide layer with high-κ material. Another advanced variant is "MONOS" ("metal–oxide–nitride–oxide–silicon"). Companies offering SONOS-based products include Cypress Semiconductor, Macronix, Toshiba, United Microelectronics Corporation and Floadia.

The 22 nm node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch for a memory cell using the process is around 22 nm. It was first demonstrated by semiconductor companies for use in RAM memory in 2008. In 2010, Toshiba began shipping 24 nm flash memory chips, and Samsung Electronics began mass-producing 20 nm flash memory chips. The first consumer-level CPU deliveries using a 22 nm process started in April 2012 with the Intel Ivy Bridge processors.

The term die shrink refers to the scaling of metal–oxide–semiconductor (MOS) devices. The act of shrinking a die creates a somewhat identical circuit using a more advanced fabrication process, usually involving an advance of lithographic nodes. This reduces overall costs for a chip company, as the absence of major architectural changes to the processor lowers research and development costs while at the same time allowing more processor dies to be manufactured on the same piece of silicon wafer, resulting in less cost per product sold.

Process variation is the naturally occurring variation in the attributes of transistors when integrated circuits are fabricated. The amount of process variation becomes particularly pronounced at smaller process nodes (<65 nm) as the variation becomes a larger percentage of the full length or width of the device and as feature sizes approach the fundamental dimensions such as the size of atoms and the wavelength of usable light for patterning lithography masks.

Z-RAM is a tradename of a now-obsolete dynamic random-access memory technology that did not require a capacitor to maintain its state. Z-RAM was developed between 2002 and 2010 by a now-defunct company named Innovative Silicon.

Polysilicon depletion effect is the phenomenon in which unwanted variation of threshold voltage of the MOSFET devices using polysilicon as gate material is observed, leading to unpredicted behavior of the electronic circuit. Because of this variation High-k Dielectric Metal Gates (HKMG) were introduced to solve the issue.

Bijan Davari is an Iranian-American engineer. He is an IBM Fellow and Vice President at IBM Thomas J Watson Research Center, Yorktown Hts, NY. His pioneering work in the miniaturization of semiconductor devices changed the world of computing. His research led to the first generation of voltage-scaled deep-submicron CMOS with sufficient performance to totally replace bipolar technology in IBM mainframes and enable new high-performance UNIX servers. As head of IBM’s Semiconductor Research Center (SRDC), he led IBM into the use of Copper interconnect, silicon on insulator (SOI), and Embedded DRAM before its rivals. He is a member of the U.S. National Academy of Engineering and is known for his seminal contributions to the field of CMOS technology. He is an IEEE Fellow, recipient of the J J Ebers Award in 2005 and IEEE Andrew S. Grove Award in 2010. At the present time, he leads the Next Generation Systems Area of research.

RF CMOS is a metal–oxide–semiconductor (MOS) integrated circuit (IC) technology that integrates radio-frequency (RF), analog and digital electronics on a mixed-signal CMOS RF circuit chip. It is widely used in modern wireless telecommunications, such as cellular networks, Bluetooth, Wi-Fi, GPS receivers, broadcasting, vehicular communication systems, and the radio transceivers in all modern mobile phones and wireless networking devices. RF CMOS technology was pioneered by Pakistani engineer Asad Ali Abidi at UCLA during the late 1980s to early 1990s, and helped bring about the wireless revolution with the introduction of digital signal processing in wireless communications. The development and design of RF CMOS devices was enabled by van der Ziel's FET RF noise model, which was published in the early 1960s and remained largely forgotten until the 1990s.

References

  1. ↑ "RFμP™ MESFET Fabrication Overview" . Retrieved 28 March 2013.
  2. ↑ J. Ervin, et al., "CMOS-Compatible SOI MESFETs With High Breakdown Voltage," IEEE Trans. Electron Devices, vol. 53, pp. 3129-3135, 2006
  3. ↑ W. Lepkowski, et al., “High Voltage SOI MESFETs at the 45nm Technology Node”, presented at IEEE Int. SOI Conf., 2012
  4. ↑ "RFμP™ MESFET Fabrication Overview" . Retrieved 28 March 2013.
  5. ↑ W. Lepkowski, et al, “40V MESFETs Fabricated on 32nm SOI CMOS”, IEEE Int. CICC Conf., 2013.
  6. ↑ "Ultra-Low-Dropout Linear Regulator". NASA Tech Briefs. Goddard Space Flight Center, Greenbelt, Maryland. Retrieved 28 March 2013.
  7. ↑ "CMOS-Compatible SOI MESFETS for Radiation-Hardened DC-to-DC Converters". NASA Tech Briefs. Goddard Space Flight Center, Greenbelt, Maryland. Retrieved 28 March 2013.
  8. ↑ Extreme Environment Electronics. Boco Raton, FL: CRC Press. 2012. pp. 49–58. ISBN   978-1439874301.
  9. ↑ Extreme Environment Electronics. Boca Raton, Florida: CRC Press. 2012. pp. 253–261, 723–732. ISBN   978-1439874301.
  10. ↑ Frontiers in Electronics. Selected Topics in Electronics and Systems. Vol. 53. 2013. pp. 167–182. doi:10.1142/8927. ISBN   978-981-4536-84-4.
  11. ↑ Douglass, Khera. "SJT Micropower - Arizona State University". NCET2.org. Archived from the original on October 4, 2013. Retrieved March 27, 2013.
  12. ↑ "Trevor Thornton - Person - Julie Ann Wrigley Global Institute of Sustainability". Julie Ann Wrigley Global Institute of Sustainability. Retrieved 2016-07-12.
  13. ↑ "SJT Micropower - Team". rfmicropower.com. Retrieved 2016-07-12.
  14. ↑ "SJT Micropower | SBIR.gov". www.sbir.gov. Retrieved 2016-07-12.
  15. ↑ "RF Micropower - Publications". rfmicropower.com. Retrieved 2016-07-12.
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