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Company type | Private |
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Industry | Semiconductors [1] |
Founded | September 2015[1] |
Founders |
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Headquarters | Santa Clara, California, U.S. [2] |
Key people | Patrick Little (CEO) [3] |
Revenue | US$38.1 million (2023) [4] |
US$−113 million (2023) [4] | |
Number of employees | c. 500 (2023) [5] |
Website | sifive |
SiFive, Inc. is an American fabless semiconductor company and provider of commercial RISC-V processors and silicon chips based on the RISC-V instruction set architecture (ISA). [6] Its products include cores, SoCs, IPs, and development boards. [7]
SiFive is one of the first companies to produce a chip that implements the RISC-V ISA. [8]
In 2015, researchers Krste Asanović, Yunsup Lee, and Andrew Waterman from the University of California Berkeley founded SiFive. [6] [7] On November 29, 2016, SiFive released the Freedom Everywhere 310 SoC and the HiFive development board. [7] This made it the first company to produce a chip that implements the RISC-V ISA since universities had already produced RISC-V processors. [7] [9]
Naveed Sherwani was appointed as the CEO in August 2017. [10] In October the same year, SiFive did a limited release of its U54-MC, which was reported to be the first RISC-V based 64-bit quad-core CPU that supported comprehensive operating systems like Linux. [11] [12]
In June 2018, SiFive acquired Open-Silicon for an undisclosed amount and retained their design capabilities for specialized chips, also called application-specific integrated circuits, or ASICs.
In February 2018, SiFive released the HiFive Unleashed, a development board containing a 64-bit SoC with four U54 cores. [13] [14]
In September 2020, Patrick Little was appointed as the CEO. [3]
In October 2020, SiFive released the HiFive Unmatched, a Mini-ITX development board with four U74-MC cores, one S7 core, 8GB DDR4 RAM, four USB 3.2 Gen1 ports, one PCI Express x16 slot, one PCIe Gen3 x4, one microSD card slot, and a Gigabit Ethernet. [15] In April 2021, the company also taped out its first system-on-chip on TSMC's N5 process technology, making it the first RISC-V-based device to be made using a 5 nm node. [16]
In June 2021, [17] Canonical announced its Ubuntu operating system supports the HiFive Unmatched and HiFive Unleashed, and the Barcelona Supercomputing Center collaborated with Codeplay Software and SiFive to implement support for the RISC-V V-extension v0.10 in the LLVM compilation infrastructure, providing vector computation capabilities through C/C++ intrinsics. [18] Reports of a potential buyout of SiFive by Intel and other companies emerged, however Intel's plans were eventually cancelled due to disagreements with SiFive. [19] [20]
In 2023, it was reported that SiFive had laid off 20% of its staff. [21]
SiFive became the main sponsor of the Cambridge United F.C. for the 2022/23 and the 2023/24 seasons. The partnership is intended to amplify both of their visions to support each other and the community, as well as establish SiFive within the city. [22] [23]
In September 2015, SiFive raised $5 million in Series A funding. In May 2017 SiFive raised $8.5 million in Series B. [24]
In April 2018, SiFive received $50.6 million Series C funding, [25] including a major amount from Intel Capital.
In June 2019, SiFive received $65.4 million in a Series D funding round [26] led by existing investors Sutter Hill Ventures, Chengwei Capital, Spark Capital, Osage University Partners and Huami, alongside new investor Qualcomm Ventures. This brought the total investment in SiFive to $125 million.
On October 23, 2019, at the Linley Fall Processor Conference, SiFive announced the release of SiFive Shield, a platform security architecture. In December 2019, the company announced the SiFive Apex cores for mission-critical markets and SiFive Intelligence cores for vector processing workloads. Later that month, Samsung also announced it will be using SiFive RISC-V cores for SoCs, automotive, and 5G applications. [27]
In January 2020, SiFive hired Chris Lattner, an American software engineer best known as the main author of LLVM and related projects such as the Clang compiler and the Swift programming language. He joined SiFive as Senior Vice President of Platform Engineering after two years at Google. [28]
In August 2020, SiFive received $60 million in a Series E funding round [29] led by investors SK Hynix and Saudi Aramco. This brought the total investment in SiFive to $186 million. That same month, SiFive announced the creation of the OpenFive business unit to focus on the creation of processor-agnostic custom SoC design. [30]
Chip company Tenstorrent, headed by former top AMD engineers, including CTO Jim Keller, licensed SiFive's Intelligence X280 processor cores in October 2020 into its homegrown AI training and inference chips. [31] Renesas Electronics also announced partnering with SiFive to design chips for vehicles. [32]
In June 2021, SiFive launched a new processor family with two core designs: P270, a Linux-capable CPU; and P550, the highest-performing RISC-V CPU. [33] [34] At the same time, Intel's Foundry Service adopted P550 for use in its Horse Creek platform, a RISC-V development platform built on Intel's newest 7 nm process node, [35] Intel 4. [36] The announcement furthered speculation of a potential acquisition of SiFive by Intel, which reportedly offered to acquire SiFive for $2 billion. [37]
As part of SiFive's “relentless innovation” program, the company announced SiFive 21G2 update for the SiFive Essential family including 11% faster U74 cores. [38]
In March 2022, SiFive received $175 million in a Series F funding round led by Coatue Management, valuing the company at over $2.5 billion. This brought the total investment in SiFive to over $350 million. [39]
In October 2023, SiFive laid off approximately 20% (~140) of its 650 employees. SiFive reiterated their commitment to existing products and lines and stated that the company is "well funded for years in the future and continue to work". [40] [41]
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DesignShare was an open source platform for building prototypes. SiFive partnered with vendors to provide IP to customers designing custom chip prototypes without paying IP fees in advance. Once chip designs were ready for mass production, customers would pay for the IP. DesignShare partners included Brite Semiconductor, Rambus, Chipus Microelectronics, and more.
Itanium is a discontinued family of 64-bit Intel microprocessors that implement the Intel Itanium architecture. The Itanium architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and Intel. Launched in June 2001, Intel initially marketed the processors for enterprise servers and high-performance computing systems. In the concept phase, engineers said "we could run circles around PowerPC...we could kill the x86." Early predictions were that IA-64 would expand to the lower-end servers, supplanting Xeon, and eventually penetrate into the personal computers, eventually to supplant reduced instruction set computing (RISC) and complex instruction set computing (CISC) architectures for all general-purpose applications.
A microprocessor is a computer processor for which the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, and control circuitry required to perform the functions of a computer's central processing unit (CPU). The IC is capable of interpreting and executing program instructions and performing arithmetic operations. The microprocessor is a multipurpose, clock-driven, register-based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, and provides results as output. Microprocessors contain both combinational logic and sequential digital logic, and operate on numbers and symbols represented in the binary number system.
MIPS Tech LLC, formerly MIPS Computer Systems, Inc. and MIPS Technologies, Inc., is an American fabless semiconductor design company that is most widely known for developing the MIPS architecture and a series of RISC CPU chips based on it. MIPS provides processor architectures and cores for digital home, networking, embedded, Internet of things and mobile applications.
PowerPC is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple–IBM–Motorola alliance, known as AIM. PowerPC, as an evolving instruction set, has been named Power ISA since 2006, while the old name lives on as a trademark for some implementations of Power Architecture–based processors.
In electronics and computer science, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler to achieve given simpler instructions.
IA-64 is the instruction set architecture (ISA) of the discontinued Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was subsequently implemented by Intel in collaboration with HP. The first Itanium processor, codenamed Merced, was released in 2001.
SuperH is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.
XScale is a microarchitecture for central processing units initially designed by Intel implementing the ARM architecture instruction set. XScale comprises several distinct families: IXP, IXC, IOP, PXA and CE, with some later models designed as system-on-a-chip (SoC). Intel sold the PXA family to Marvell Technology Group in June 2006. Marvell then extended the brand to include processors with other microarchitectures, like Arm's Cortex.
OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community.
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The ETRAX CRIS is a RISC ISA and series of CPUs designed and manufactured by Axis Communications for use in embedded systems since 1993. The name is an acronym of the chip's features: Ethernet, Token Ring, AXis - Code Reduced Instruction Set. Token Ring support has been taken out from the latest chips as it has become obsolete.
Tilera Corporation was a fabless semiconductor company focusing on manycore embedded processor design. The company shipped multiple processors in the TILE64, TILEPro64, and TILE-Gx lines.
Arm Holdings plc is a British semiconductor and software design company based in Cambridge, England, whose primary business is the design of central processing unit (CPU) cores that implement the ARM architecture family of instruction sets. It also designs other chips, provides software development tools under the DS-5, RealView and Keil brands, and provides systems and platforms, system-on-a-chip (SoC) infrastructure and software. As a "holding" company, it also holds shares of other companies. Since 2016, it has been majority owned by Japanese conglomerate SoftBank Group.
Heterogeneous computing refers to systems that use more than one kind of processor or core. These systems gain performance or energy efficiency not just by adding the same type of processors, but by adding dissimilar coprocessors, usually incorporating specialized processing capabilities to handle particular tasks.
RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. Many companies are offering or have announced RISC-V hardware; open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.
Since 1985, many processors implementing some version of the MIPS architecture have been designed and used widely.
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