Extended Display Identification Data

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Extended Display Identification Data (EDID) and Enhanced EDID (E-EDID) are metadata formats for display devices to describe their capabilities to a video source (e.g., graphics card or set-top box). The data format is defined by a standard published by the Video Electronics Standards Association (VESA).

Contents

The EDID data structure includes manufacturer name and serial number, product type, phosphor or filter type (as chromaticity data), timings supported by the display, display size, luminance data and (for digital displays only) pixel mapping data.

DisplayID is a VESA standard targeted to replace EDID and E-EDID extensions with a uniform format suited for both PC monitor and consumer electronics devices.

Background

EDID structure (base block) versions range from v1.0 to v1.4; all these define upwards-compatible 128-byte structures. Version 2.0 defined a new 256-byte structure but it has been deprecated and replaced by E-EDID which supports multiple extension blocks.[ citation needed ] HDMI versions 1.0–1.3c use E-EDID v1.3. [1]

Before Display Data Channel (DDC) and EDID were defined, there was no standard way for a graphics card to know what kind of display device it was connected to. Some VGA connectors in personal computers provided a basic form of identification by connecting one, two or three pins to ground, but this coding was not standardized.

This problem is solved by EDID and DDC, as it enables the display to send information to the graphics card it is connected to. The transmission of EDID information usually uses the Display Data Channel protocol, specifically DDC2B, which is based on I²C-bus (DDC1 used a different serial format which never gained popularity). The data is transmitted via the cable connecting the display and the graphics card; VGA, DVI, DisplayPort and HDMI are supported.[ citation needed ]

The EDID is often stored in the monitor in the firmware chip called serial EEPROM (electrically erasable programmable read-only memory) and is accessible via the I²C-bus at address 0x50. The EDID PROM can often be read by the host PC even if the display itself is turned off.

Many software packages can read and display the EDID information, such as read-edid [2] for Linux and DOS, PowerStrip [3] for Microsoft Windows and the X.Org Server for Linux and BSD unix. Mac OS X natively reads EDID information and programs such as SwitchResX [4] or DisplayConfigX [5] can display the information as well as use it to define custom resolutions.

E-EDID was introduced at the same time as E-DDC, which supports multiple extensions blocks and deprecated EDID version 2.0 structure (it can be incorporated in E-EDID as an optional extension block). Data fields for preferred timing, range limits, and monitor name are required in E-EDID. E-EDID also adds support for the Dual GTF curve concept and partially changed the encoding of aspect ratio within the standard timings.

With the use of extensions, E-EDID structure can be extended up to 32 KiB, because the E-DDC added the capability to address multiple (up to 128) 256 byte segments.

EDID Extensions assigned by VESA

Revision history

Limitations

Some graphics card drivers have historically coped poorly with the EDID, using only its standard timing descriptors rather than its Detailed Timing Descriptors (DTDs). Even in cases where the DTDs were read, the drivers are/were still often limited by the standard timing descriptor limitation that the horizontal/vertical resolutions must be evenly divisible by 8. This means that many graphics cards cannot express the native resolutions of the most common wide screen flat panel displays and liquid crystal display televisions. The number of vertical pixels is calculated from the horizontal resolution and the selected aspect ratio. To be fully expressible, the size of wide screen display must thus be a multiple of 16×9 pixels. For 1366×768 pixel Wide XGA panels the nearest resolution expressible in the EDID standard timing descriptor syntax is 1360×765 pixels, typically leading to 3 pixel thin black bars. Specifying 1368 pixels as the screen width would yield an unnatural screen height of 769.5 pixels.

Many Wide XGA panels do not advertise their native resolution in the standard timing descriptors, instead offering only a resolution of 1280×768. Some panels advertise a resolution only slightly smaller than the native, such as 1360×765. For these panels to be able to show a pixel perfect image, the EDID data must be ignored by the display driver or the driver must correctly interpret the DTD and be able to resolve resolutions whose size is not divisible by 8. Special programs are available to override the standard timing descriptors from EDID data. Even this is not always possible, as some vendors' graphics drivers (notably those of Intel) require specific registry hacks to implement custom resolutions, which can make it very difficult to use the screen's native resolution. [7]

EDID 1.4 data format

Structure, version 1.4

EDID structure, version 1.4 [8] [9]
BytesDescription
0–19Header information
0–7Fixed header pattern: 00 FF FF FF FF FF FF 00
8–9Manufacturer ID. This is a legacy Plug and Play ID assigned by UEFI forum, which is a big-endian 16-bit value made up of three 5-bit letters: 00001, A; 00010, B; ...; 11010, Z. E.g.: 24 4d, 0010010001001101, "IBM"; "PHL" (Philips).
Bit 150 = reserved
Bits 14–10First letter of manufacturer ID (byte 8, bits 6–2)
Bits 9–5Second letter of manufacturer ID (byte 8, bit 1 through byte 9 bit 5)
Bits 4–0Third letter of manufacturer ID (byte 9 bits 4–0)
10–11Manufacturer product code. 16-bit hex number, little-endian. For Example, "PHL" + "C0CF".
12–15Serial number. 32 bits, little-endian.
16Week of manufacture; or FF model year flag. Week numbering is not consistent between manufacturers.
17Year of manufacture, or year of model, if model year flag is set. Year = datavalue + 1990.
18EDID version, usually 01 (for 1.3 and 1.4)
19EDID revision, usually 03 (for 1.3) or 04 (for 1.4)
20–24Basic display parameters
20Video input parameters bitmap
Bit 7 = 1Digital input. If set, the following bit definitions apply:
Bits 6–4Bit depth:

000 = undefined
001 = 6
010 = 8
011 = 10
100 = 12
101 = 14
110 = 16 bits per color
111 = reserved

Bits 3–0Video interface:

0000 = undefined
0001 = DVI
0010 = HDMIa
0011 = HDMIb
0100 = MDDI
0101 = DisplayPort

Bit 7 = 0Analog input. If clear, the following bit definitions apply:
Bits 6–5Video white and sync levels, relative to blank:

00 = +0.7/−0.3 V
01 = +0.714/−0.286 V
10 = +1.0/−0.4 V
11 = +0.7/0 V (EVC)

Bit 4Blank-to-black setup (pedestal) expected
Bit 3Separate sync supported
Bit 2Composite sync (on HSync) supported
Bit 1 Sync on green supported
Bit 0VSync pulse must be serrated when composite or sync-on-green is used.
21Horizontal screen size, in centimetres (range 1–255). If vertical screen size is 0, landscape aspect ratio (range 1.00–3.54), datavalue = (AR×100) − 99 (example: 16:9, 79; 4:3, 34.)
22Vertical screen size, in centimetres. If horizontal screen size is 0, portrait aspect ratio (range 0.28–0.99), datavalue = (100/AR) − 99 (example: 9:16, 79; 3:4, 34.) If both bytes are 0, screen size and aspect ratio are undefined (e.g. projector)
23Display gamma, factory default (range 1.00–3.54), datavalue = (gamma×100) − 100 = (gamma − 1)×100. If 255, gamma is defined by DI-EXT block.
24Supported features bitmap
Bit 7 DPMS standby supported
Bit 6DPMS suspend supported
Bit 5DPMS active-off supported
Bits 4–3Display type (digital):

00 = RGB 4:4:4
01 = RGB 4:4:4 + YCrCb 4:4:4
10 = RGB 4:4:4 + YCrCb 4:2:2
11 = RGB 4:4:4 + YCrCb 4:4:4 + YCrCb 4:2:2

Display type (analog):

00 = monochrome or grayscale
01 = RGB color
10 = non-RGB color
11 = undefined

Bit 2Standard sRGB colour space. Bytes 25–34 must contain sRGB standard values.
Bit 1Preferred timing mode specified in descriptor block 1. For EDID 1.3+ the preferred timing mode is always in the first Detailed Timing Descriptor. In that case, this bit specifies whether the preferred timing mode includes native pixel format and refresh rate.
Bit 0Continuous timings with GTF or CVT
25–34Chromaticity coordinates.
10-bit 2° CIE 1931 xy coordinates for red, green, blue, and white point
25Red and green least-significant bits (2−9, 2−10)
Bits 7–6Red x value least-significant 2 bits
Bits 5–4Red y value least-significant 2 bits
Bits 3–2Green x value least-significant 2 bits
Bits 1–0Green y value least-significant 2 bits
26Blue and white least-significant 2 bits
27Red x value most significant 8 bits (2−1, ..., 2−8). 0–255 encodes fractional 0–0.996 (255/256); 0–0.999 (1023/1024) with lsbits
28Red y value most significant 8 bits
29–30Green x and y value most significant 8 bits
31–32Blue x and y value most significant 8 bits
33–34Default white point x and y value most significant 8 bits
35–37Established timing bitmap. Supported bitmap for (formerly) very common timing modes.
35Bit 7720×400 @ 70 Hz (VGA)
Bit 6720×400 @ 88 Hz (XGA)
Bit 5640×480 @ 60 Hz (VGA)
Bit 4640×480 @ 67 Hz (Apple Macintosh II)
Bit 3640×480 @ 72 Hz
Bit 2640×480 @ 75 Hz
Bit 1800×600 @ 56 Hz
Bit 0800×600 @ 60 Hz
36Bit 7800×600 @ 72 Hz
Bit 6800×600 @ 75 Hz
Bit 5832×624 @ 75 Hz (Apple Macintosh II)
Bit 41024×768 @ 87 Hz, interlaced (1024×768i)
Bit 31024×768 @ 60 Hz
Bit 21024×768 @ 70 Hz
Bit 11024×768 @ 75 Hz
Bit 01280×1024 @ 75 Hz
37Bit 71152x870 @ 75 Hz (Apple Macintosh II)
Bits 6–0Other manufacturer-specific display modes
38–53Standard timing information. Up to 8 2-byte fields describing standard display modes.
Unused fields are filled with 01 01 hex. The following definitions apply in each record:
38Standard timing 1: X resolution, 00 = reserved; otherwise, (datavalue + 31) × 8 (256–2288 pixels).
39Bits 7–6Standard timing 1: Image aspect ratio:

00 = 16:10
01 = 4:3
10 = 5:4
11 = 16:9
(Versions prior to 1.3 defined 00 as 1:1.)

Bits 5–0Vertical frequency, datavalue + 60 (60–123 Hz)
40-41Standard timing 2
42-43Standard timing 3
44-45Standard timing 4
46-47Standard timing 5
48-49Standard timing 6
50-51Standard timing 7
52-53Standard timing 8
54–125Display timing descriptor followed by display/monitor descriptors
54–71Preferred timing descriptor18 byte detailed timing descriptors or display descriptors
72–89Descriptor 2
90–107Descriptor 3
108–125Descriptor 4
126-127Extension flag and checksum
126Number of extensions to follow. 0 if no extensions.
127Checksum. Sum of all 128 bytes should equal 0 (mod 256).

Detailed Timing Descriptor

EDID Detailed Timing Descriptor [8]
BytesDescription
0–1Pixel clock. 00 = reserved; otherwise in 10 kHz units (0.01–655.35 MHz, little-endian).
2Horizontal active pixels 8 lsbits (0–255)
3 Horizontal blanking pixels 8 lsbits (0–255) End of active to start of next active.
4Bits 7–4Horizontal active pixels 4 msbits (0–15)
Bits 3–0Horizontal blanking pixels 4 msbits (0–15)
5Vertical active lines 8 lsbits (0–255)
6Vertical blanking lines 8 lsbits (0–255)
7Bits 7–4Vertical active lines 4 msbits (0–15)
Bits 3–0Vertical blanking lines 4 msbits (0–15)
8Horizontal front porch (sync offset) pixels 8 lsbits (0–255) From blanking start
9Horizontal sync pulse width pixels 8 lsbits (0–255)
10Bits 7–4Vertical front porch (sync offset) lines 4 lsbits (0–15)
Bits 3–0Vertical sync pulse width lines 4 lsbits (0–15)
11Bits 7–6Horizontal front porch (sync offset) pixels 2 msbits (0–3)
Bits 5–4Horizontal sync pulse width pixels 2 msbits (0–3)
Bits 3–2Vertical front porch (sync offset) lines 2 msbits (0–3)
Bits 1–0Vertical sync pulse width lines 2 msbits (0–3)
12Horizontal image size, mm, 8 lsbits (0–255 mm, 161 in)
13Vertical image size, mm, 8 lsbits (0–255 mm, 161 in)
14Bits 7–4Horizontal image size, mm, 4 msbits (0–15)
Bits 3–0Vertical image size, mm, 4 msbits (0–15)
15Horizontal border pixels (one side; total is twice this) (0–255)
16Vertical border lines (one side; total is twice this) (0–255)
17Features bitmap
Bit 7Signal Interface Type:

0 = non-interlaced;
1 = interlaced.

Bits 6–5Stereo mode (combine bits 6–5 with bit 0):

00x = none, bit 0 is "don't care";
010 = field sequential, right during stereo sync;
100 = field sequential, left during stereo sync;
011 = 2-way interleaved, right image on even lines;
101 = 2-way interleaved, left image on even lines;
110 = 4-way interleaved;
111 = side-by-side interleaved.

Bit 4 = 0Analog sync.
If set, the following bit definitions apply:
Bit 3Sync type:

0 = analog composite;
1 = bipolar analog composite.

Bit 2Serration:

0 = without serrations;
1 = with serrations (H-sync during V-sync).

Bit 1Sync on red and blue lines additionally to green

0 = sync on green signal only;
1 = sync on all three (RGB) video signals.

Bits 4–3 = 10Digital sync., composite (on HSync).
If set, the following bit definitions apply:
Bit 2Serration

0 = without serration;
1 = with serration (H-sync during V-sync).

Bit 1Horizontal sync polarity:

0 = negative;
1 = positive.

Bits 4–3 = 11Digital sync., separate
If set, the following bit definitions apply:
Bit 2Vertical sync polarity:

0 = negative;
1 = positive.

Bit 1Horizontal sync polarity:

0 = negative;
1 = positive.

Bit 0Stereo mode (combines with bits 6–5)

When used for another descriptor, the pixel clock and some other bytes are set to 0:

Monitor Descriptors

EDID Monitor Descriptors [8]
BytesDescription
0–10 = Monitor Descriptor (cf. Detailed Timing Descriptor).
20 = reserved
3Descriptor type. FA–FF currently defined. 00–0F reserved for vendors.
40 = reserved, except for Display Range Limits Descriptor.
5–17Defined by descriptor type. If text, code page 437 text, terminated (if less than 13 bytes) with LF and padded with SP.

Currently defined descriptor types are:

Display Range Limits

Descriptor

EDID Display Range Limits Descriptor [8]
BytesDescription
0–100 00 = Display Descriptor
200 = reserved
3FD = Display Range Limits Descriptor
4Offsets for display range limits
Bits 7–400 = reserved
Bits 3–2Horizontal rate offsets:

00 = none;
10 = +255 kHz for max. rate;
11 = +255 kHz for max. and min. rates.

Bits 1–0Vertical rate offsets:

00 = none;
10 = +255 Hz for max. rate;
11 = +255 Hz for max. and min. rates.

5Minimumvertical field rate (1–255 Hz; 256–510 Hz, if offset).
6Maximum
7Minimumhorizontal line rate (1–255 kHz; 256–510 kHz, if offset).
8Maximum
9Maximum pixel clock rate, rounded up to 10 MHz multiple (10–2550 MHz).
10Extended timing information type:

00 = Default GTF (when basic display parameters byte 24, bit 0 is set).
01 = No timing information.
02 = Secondary GTF supported, parameters as follows.
04 = CVT (when basic display parameters byte 24, bit 0 is set), parameters as follows.

11–17Video timing parameters (if byte 10 is 00 or 01, padded with 0A 20 20 20 20 20 20).

With GTF secondary curve

EDID Display Range Limits with GTF Secondary curve [8]
BytesDescription
1002
1100 = reserved
12Start frequency for secondary curve, divided by 2 kHz (0–510 kHz)
13GTF C value, multiplied by 2 (0–127.5)
14–15GTF M value (0–65535, little-endian)
16GTF K value (0–255)
17GTF J value, multiplied by 2 (0–127.5)

With CVT support

EDID Display Range Limits with CVT support [8]
BytesDescription
1004
11Bits 7–4CVT major version (1–15)
Bits 3–0CVT minor version (0–15)
12Bits 7–2Additional clock precision in 0.25 MHz increments
(to be subtracted from byte 9 maximum pixel clock rate)
Bits 1–0Maximum active pixels per line, 2-bit msb
13Maximum active pixels per line, 8-bit lsb (no limit if 0)
14Aspect ratio bitmap
Bit 74∶3
Bit 616∶9
Bit 516∶10
Bit 45∶4
Bit 315∶9
Bits 2–0000 = reserved
15Bits 7–5Aspect ratio preference:

000 = 4∶3
001 = 16∶9
010 = 16∶10
011 = 5∶4
100 = 15∶9

Bit 4CVT-RB reduced blanking (preferred)
Bit 3CVT standard blanking
Bits 2–0000 = reserved
16Scaling support bitmap
Bit 7Horizontal shrink
Bit 6Horizontal stretch
Bit 5Vertical shrink
Bit 4Vertical stretch
Bits 3–00000 = reserved
17Preferred vertical refresh rate (1–255)

Additional white point descriptor

EDID additional white point descriptor [8]
BytesDescription
0–400 00 00FB00
5White point index number (1–255). Usually 1; 0 indicates descriptor not used.
6White point CIE xy coordinates least-significant bits (like EDID byte 26)
Bits 7–4000 = reserved
Bits 3–2White point x value least-significant 2 bits
Bits 1–0White point y value least-significant 2 bits
7White point x value most significant 8 bits (like EDID byte 27)
8White point y value most significant 8 bits (like EDID byte 28)
9datavalue = (gamma − 1)×100 (1.0–3.54, like EDID byte 23)
10–14Second descriptor. Index number starts with 2; if 0 = unused
15–17Unused, padded with 0A 20 20.

Color management data descriptor

EDID color management data descriptor [8]
BytesDescription
0–400 00 00F900
5Version: 03
6Red a3 lsb
7Red a3 msb
8Red a2 lsb
9Red a2 msb
10Green a3 lsb
11Green a3 msb
12Green a2 lsb
13Green a2 msb
14Blue a3 lsb
15Blue a3 msb
16Blue a2 lsb
17Blue a2 msb

CVT 3-byte timing codes descriptor

EDID CVT 3-byte timing codes descriptor [8]
BytesDescription
0–400 00 00F800
5Version: 01
6-8CVT timing descriptor #1
6Addressable lines per field 8-bit lsb
7Bits 7–4Addressable lines per field 4-bit msb
Bits 3–2Aspect ratio:

00 = 4∶3
01 = 16∶9
10 = 16∶10
11 = 15∶9

Bits 1–000 = reserved
8Bit 70 = reserved
Bits 6–5Preferred vertical rate:

00: 50 Hz
01: 60 Hz
10: 75 Hz
11: 85 Hz

Vertical rate bitmap
Bit 450 Hz CVT
Bit 360 Hz CVT
Bit 275 Hz CVT
Bit 185 Hz CVT
Bit 060 Hz CVT reduced blanking
9–11CVT timing descriptor #2
12–14CVT timing descriptor #3
15–17CVT timing descriptor #4


Additional standard timings

EDID Additional standard timings 3 [8]
BytesDescription
0–400 00 00F700
5Version: 10
6Bit 7640×350@ 85 Hz
Bit 6640×400
Bit 5720×400
Bit 4640×480
Bit 3848×480@ 60 Hz
Bit 2800×600@ 85 Hz
Bit 11024×768
Bit 01152×864
7Bit 71280×768@ 60 Hz (CVT-RB)
Bit 6@ 60 Hz
Bit 5@ 75 Hz
Bit 4@ 85 Hz
Bit 31280×960@ 60 Hz
Bit 2@ 85 Hz
Bit 11280×1024@ 60 Hz
Bit 0@ 85 Hz
8Bit 71360×768@ 60 Hz (CVT-RB)
Bit 61280×768@ 60 Hz
Bit 51440×900@ 60 Hz (CVT-RB)
Bit 4@ 75 Hz
Bit 3@ 85 Hz
Bit 21400×1050@ 60 Hz (CVT-RB)
Bit 1@ 60 Hz
Bit 0@ 75 Hz
9Bit 7@ 85 Hz
Bit 61680×1050@ 60 Hz (CVT-RB)
Bit 5@ 60 Hz
Bit 4@ 75 Hz
Bit 3@ 85 Hz
Bit 21600×1200@ 60 Hz
Bit 1@ 65 Hz
Bit 0@ 70 Hz
10Bit 7@ 75 Hz
Bit 6@ 85 Hz
Bit 51792×1344@ 60 Hz
Bit 4@ 75 Hz
Bit 31856×1392@ 60 Hz
Bit 2@ 75 Hz
Bit 11920×1200@ 60 Hz (CVT-RB)
Bit 0@ 60 Hz
11Bit 7@ 75 Hz
Bit 6@ 85 Hz
Bit 51920×1440@ 60 Hz
Bit 4@ 75 Hz
Bits 3–00000 = reserved
12–17Unused, must be 0.

CTA EDID Timing Extension Block

The CTA EDID Extension was first introduced in EIA/CEA-861.

CTA-861 Standard

The ANSI/CTA-861 industry standard, which according to CTA is now their "Most Popular Standard", [10] has since been updated several times, most notably with the 861-B revision (published in May 2002, which added version 3 of the extension, adding Short Video Descriptors and advanced audio capability/configuration information), 861-D (published in July 2006 and containing updates to the audio segments), 861-E in March 2008, [11] 861-F, which was published on June 4, 2013, [12] 861-H in December 2020, [13] and, most recently, 861-I, which was published in February 2023. [14] Coinciding with the publication of CEA-861-F in 2013, Brian Markwalter, senior vice president, research and standards, stated: "The new edition includes a number of noteworthy enhancements, including support for several new Ultra HD and widescreen video formats and additional colorimetry schemes.” [15]

Version CTA-861-G, [16] originally published in November 2016, was made available for free in November 2017, along with updated versions -E and -F, after some necessary changes due to a trademark complaint. All CTA standards are free to everyone since May 2018. [17] [18]

The most recent version is CTA-861-I, [19] published in February 2023, available for free after registration. It combines the previous version, CTA-861-H, [20] from January 2021 with an amendment, CTA-861.6, [21] published in February 2022 and includes a new formula to calculate Video Timing Formats, OVT. [22] Other changes include a new annex to elaborate on the audio speaker room configuration system that was introduced with the 861.2 amendment, and some general clarifications and formatting cleanup.

CTA Extension Block

Version 1 of the extension block (as defined in CEA−861) allowed the specification of video timings only through the use of 18-byte Detailed Timing Descriptors (DTD) (as detailed in EDID 1.3 data format above). DTD timings are listed in order of preference in the CEA EDID Timing Extension.

Version 2 (as defined in 861-A) added the capability to designate a number of DTDs as "native" (i.e., matching the resolution of the display) and also included some "basic discovery" functionality for whether the display device contains support for "basic audio", YCBCR pixel formats, and underscan.

Version 3 (from the 861-B spec onward) allows two different ways to specify digital video timing formats: As in Version 1 & 2 by the use of 18-byte DTDs, or by the use of the Short Video Descriptor (SVD) (see below). HDMI 1.0–1.3c uses this[ which? ] version.

Version 3 also defines a format for a collection of data blocks, which in turn can contain a number of individual descriptors. This Data Block Collection (DBC) initially had four types of Data Blocks (DBs): Video Data Blocks containing the aforementioned Short Video Descriptor (SVD), Audio Data Blocks containing Short Audio Descriptors (SAD), Speaker Allocation Data Blocks containing information about the speaker configuration of the display device, and Vendor Specific Data Blocks which can contain information specific to a given vendor's use. Subsequent versions of CTA-861 defined additional data blocks.

CTA Extension data format

ByteDescription
0Extension tag (which kind of extension block this is); 02 for CTA EDID
1Revision number (version number); 03 for version 3
2Byte number (decimal) within this block where the 18-byte DTDs begin. If no non-DTD data is present in this extension block, the value should be set to 04 (the byte after next). If set to 00, there are no DTDs present in this block and no non-DTD data.
3With version 2 and up: number of Native DTDs present, other information. Reserved with earlier versions.
Bit 71 if display supports underscan, 0 if not
Bit 61 if display supports basic audio, 0 if not
Bit 51 if display supports YCBCR 4∶4∶4, 0 if not
Bit 41 if display supports YCBCR 4∶2∶2, 0 if not
Bit 3–0Total number of native formats in the DTDs included in this block
4–126With version 3 and up: Data Block Collection, starting at byte 4, ending immediately before the byte specified in byte 2. If byte 2 is 04, the collection is of zero length (i.e. not present). If byte 2 is 00, no DTDs are present and the DBC takes up the entire remaining EDID block ahead of the checksum. Reserved with earlier versions.
18-byte descriptors, starting at the byte specified in byte 2 (if non-zero). Consecutive descriptors are present while the bytes 0–1 of each are not 00 00.
Padding, from the absence of an 18-byte descriptor onwards; must be 00.
127Checksum. Value such that the one-byte sum of all 128 bytes is 00.

The Data Block Collection contains one or more data blocks detailing video, audio, and speaker placement information about the display. The blocks can be placed in any order, and the initial byte of each block defines both its type and its length:

Data block header
ByteDescription
0Bit 7–5Block Type Tag
  • 001 1: Audio (ADB, containing SADs)
  • 010 2: Video (VDB, containing SVDs)
  • 011 3: Vendor Specific (VSDB)
  • 100 4: Speaker Allocation (SADB)
  • 101 5: VESA Display Transfer Characteristic (VESA DTCDB)
  • 110 6: Video Format (VFDB, containing VFDs)
  • 111 7: Use Extended Tag
Bit 4–0Total number of bytes in this block following this byte.

If the Tag code is 7, an Extended Tag Code is present in the first payload byte of the data block, and the second payload byte represents the first payload byte of the extended data block.

Extended Block Type Tag
ByteDescription
1Bit 7–0Extended Block Type Tag
  • 00000000 0: Video Capability (VCDB)
  • 00000001 1: Vendor Specific Video (VSVDB)
  • 00000010 2: VESA Display Device (VESA DDDB)
  • 00000011 3: reserved for VESA
  • 00000100 4: reserved for HDMI
  • 00000101 5: Colorimetry (CDB)
  • 00000110 6: HDR Static Metadata (HDR SMDB)
  • 00000111 7: HDR Dynamic Metadata (HDR DMDB)
  • 00001000 8: Native Video Resolution (NVRDB)
  • 9-12: reserved for video
  • 00001101 13: Video Format Preference (VFPDB)
  • 00001110 14: YCBCR 4:2:0 Video (Y420VDB)
  • 00001111 15: YCBCR 4:2:0 Capability Map (Y420CMDB)
  • 00010000 16: reserved for CTA (CTA MAF)
  • 00010001 17: Vendor Specific Audio (VSADB)
  • 00010010 18: HDMI Audio (HDMI ADB)
  • 00010011 19: Room Configuration (RCDB)
  • 00010100 20: Speaker Location (SLDB, containing SLDs)
  • 21-31: reserved for audio
  • 00100000 32: InfoFrame (IFDB)
  • 00100001 33: reserved
  • 00100010 34: Type VII video timing (T7VTDB)
  • 00100011 35: Type VIII video timing (T8VTDB)
  • 36-41: reserved
  • 00101010 42: Type X video timing (T10VTDB)
  • 42-119: reserved
  • 01111000 120: HDMI Forum EDID Extension Override (HF-EEODB)
  • 01111001 121: HDMI Forum Sink Capbility (HF-SCDB)
  • 01111010 122: HDMI Forum Source-Based Tone Mapping (HF-SBTMDB)
  • 123-127: reserved for HDMI
  • else: reserved

Once one data block has ended, the next byte is assumed to be the beginning of the next data block. This is the case until the byte (designated in byte 2, above) where the DTDs are known to begin.

CTA Data Blocks

Audio Data Blocks contain one or more 3-byte Short Audio Descriptors (SADs). Each SAD details audio format, channel number, and bitrate/resolution capabilities of the display as follows:

Short Audio Descriptor
ByteDescription
0Data block header
1Format and number of channels:
Bit 7Reserved, 0
Bit 6–3Audio format code
Bit 2–0Number of channels minus 1
  • 000 1 channel
  • 001 2 channels
  • 010 3 channels
  • 011 4 channels
  • 100 5 channels
  • 101 6 channels
  • 110 7 channels
  • 111 8 channels
2Sampling frequencies (kHz) supported:
Bit 7Reserved, 0
Bit 6192
Bit 5176
Bit 496
Bit 388
Bit 248
Bit 144.1
Bit 032
3Bitrate / format dependent:
For codec 1, LPCM:
Bits 7–3Reserved
Bit 224-bit depth
Bit 120-bit depth
Bit 016-bit depth
For audio format codecs 2–8, the maximum supported bitrate in bit/s, divided by 8000.
For audio format codecs 9–14, format dependent value.
For audio format codec 15 (Extension):
Bit 7–3Audio format extended code
Bits 2–0format dependent value

Video Data Blocks will contain one or more 1-byte Short Video Descriptors (SVDs).

ByteDescription
0Data block header
1Bit 71 to designate that this should be considered a "native" resolution, 0 for non-native. Used for 7-bit VICs 1 – 64 only, otherwise this is the MSB for the 8-bit VIC.
Bit 6–0VIC: Index value to a table of standard resolutions/timings from EIA/CEA-861:
EIA/CEA-861 standard resolutions and timings
VICShort nameAspect ratioClockActiveTotalField rate (Hz)
DARPARPixel (MHz)V (Hz)H (kHz)HVHV
1DMT06594∶31∶125.17559.9431.46964048080052560
2480p4∶38∶92759.9431.46972048085852560
3480pH16∶932∶272759.9431.46972048085852560
4720p16∶91∶174.256045.01280720165075060
51080i16∶91∶174.256033.7519205402200562.560
6480i4∶38∶92759.9415.73414402401716262.560
7480iH16∶932∶272759.9415.73414402401716262.560
8240p4∶34∶92759.82615.73414402401716262.560
9240pH16∶916∶272759.82615.73414402401716262.560
10480i4x4∶32:9-20:95459.9415.73428802403432262.560
11480i4xH16∶98:27-80:275459.9415.73428802403432262.560
12240p4x4∶31:9-10:9546015.73428802403432262.560
13240p4xH16∶94:27-40:27546015.73428802403432262.560
14480p2x4∶34:9, 8∶95459.9431.4691440480171652560
15480p2xH16∶916:27, 32∶275459.9431.4691440480171652560
161080p16∶91∶1148.56067.5192010802200112560
17576p4∶316∶15275031.2572057686462550
18576pH16∶964∶45275031.2572057686462550
19720p5016∶91∶174.255037.51280720198075050
201080i2516∶91∶174.255028.12519205402640562.550
21576i4∶316∶15275015.62514402881728312.550
22576iH16∶964∶45275015.62514402881728312.550
23288p4∶38∶15275015.6251440288172831350
24288pH16∶932∶45275015.6251440288172831350
25576i4x4∶32:15-20:15545015.62528802883456312.550
26576i4xH16∶916:45-160:45545015.62528802883456312.550
27288p4x4∶31:15-10:15545015.6252880288345631350
28288p4xH16∶98:45-80:45545015.6252880288345631350
29576p2x4∶38:15, 16∶15545031.251440576172862550
30576p2xH16∶932:45, 64∶45545031.251440576172862550
311080p5016∶91∶1148.55056.25192010802640112550
321080p2416∶91∶174.2523.98/24271920108027501125Low
331080p2516∶91∶174.252528.1251920108026401125Low
341080p3016∶91∶174.2529.97/3033.751920108022001125Low
35480p4x4∶32:9, 4:9, 8∶910859.9431.46928802403432262.560
36480p4xH16∶98:27, 16:27, 32∶2710859.9431.46928802403432262.560
37576p4x4∶34:15, 8:15, 16∶151085031.252880576345662550
38576p4xH16∶916:45, 32:45, 64∶451085031.252880576345662550
391080i2516∶91∶1725031.251920540230462550
401080i5016∶91∶1148.510056.2519205402640562.5100
41720p10016∶91∶1148.510045.012807201980750100
42576p1004∶316∶155410062.5720576864625100
43576p100H16∶964∶455410062.5720576864625100
44576i504∶316∶155410031.2514405761728625100
45576i50H16∶964∶455410031.2514405761728625100
461080i6016∶91∶1148.5119.88/12067.519205402200562.5120
47720p12016∶91∶1148.5119.88/12090.012807201650750120
48480p1194∶38∶954119.88/12062.937720480858525120
49480p119H16∶932∶2754119.88/12062.937720480858525120
50480i594∶316∶1554119.88/12031.46914404801716525120
51480i59H16∶964∶4554119.88/12031.46914404801716525120
52576p2004∶316∶15108200125.0720576864625200
53576p200H16∶964∶45108200125.0720576864625200
54576i1004∶316∶1510820062.514402881728312.5200
55576i100H16∶964∶4510820062.514402881728312.5200
56480p2394∶38∶9108239.76125.874720480858525240
57480p239H16∶932∶27108239.76125.874720480858525240
58480i1194∶38∶9108239.7662.93714402401716262.5240
59480i119H16∶932∶27108239.7662.93714402401716262.5240
60720p2416∶91∶159.423.98/2418.012807203300750Low
61720p2516∶91∶174.252518.7512807203960750Low
62720p3016∶91∶174.2529.97/3022.512807203300750Low
631080p12016∶91∶1297119.88/120135.01920108022001125120
641080p10016∶91∶1297100112.51920108026401125100
65720p2464∶274∶359.423.98/2418.012807203300750Low
66720p2564∶274∶374.252518.7512807203960750Low
67720p3064∶274∶374.2529.97/3022.512807203300750Low
68720p5064∶274∶374.255037.51280720198075050
69720p64∶274∶374.256045.01650750165075060
70720p10064∶274∶3148.510075.012807201980750100
71720p12064∶274∶3148.5119.88/12090.012807201650750120
721080p2464∶274∶374.2523.98/24271920108027501125Low
731080p2564∶274∶374.252528.1251920108026401125Low
741080p3064∶274∶374.2529.97/3033.751920108022001125Low
751080p5064∶274∶3148.55056.25192010802640112550
761080p64∶274∶3148.56067.5192010802200112560
771080p10064∶274∶3297.0100112.51920108026401125100
781080p12064∶274∶3297.0119.88/120135.01920108022001125120
79720p2x2464∶2764∶6359.423.98/2418.016807203300750Low
80720p2x2564∶2764∶6359.42518.7516807203168750Low
81720p2x3064∶2764∶6359.429.97/3022.516807202640750Low
82720p2x5064∶2764∶6382.55037.51680720220075050
83720p2x64∶2764∶63996045.01680720220075060
84720p2x10064∶2764∶6316510082.516807202000825100
85720p2x12064∶2764∶63198119.88/12099.016807202000825120
861080p2x2464∶271∶19923.98/2426.42560108037501100Low
871080p2x2564∶271∶1902528.1252560108032001125Low
881080p2x3064∶271∶1118.829.97/3033.752560108035201125Low
891080p2x5064∶271∶1185.6255056.25256010803000112550
901080p2x64∶271∶11986066.0256010803000110060
911080p2x10064∶271∶1371.25100125.02560108029701250100
921080p2x12064∶271∶1495119.88/120150.02560108033001250120
932160p2416∶91∶129723.98/24543840216055002250Low
942160p2516∶91∶12972556.253840216052802250Low
952160p3016∶91∶129729.97/3067.53840216044002250Low
962160p5016∶91∶159450112.5384021605280225050
972160p6016∶91∶159460135.0384021604400225060
982160p24256∶1351∶129723.98/2467.54096216055002250Low
992160p25256∶1351∶129725112.54096216052802250Low
1002160p30256∶1351∶129729.97/30135.04096216044002250Low
1012160p50256∶1351∶159450112.5409621605280225050
1022160p256∶1351∶159460135.0409621604400225060
1032160p2464∶274∶329723.98/2467.53840216055002250Low
1042160p2564∶274∶329725112.53840216052802250Low
1052160p3064∶274∶329729.97/30135.03840216044002250Low
1062160p5064∶274∶359450112.5384021605280225050
1072160p64∶274∶359460135.0384021604400225060
108720p4816∶91∶19047.96/4836.012807202500750Low
109720p4864∶274∶39047.96/4836.012807202500750Low
110720p2x4864∶2764∶639947.96/4836.016807202750825Low
1111080p4816∶91∶1148.547.96/48541920108027501125Low
1121080p4864∶274∶3148.547.96/48541920108027501125Low
1131080p2x4864∶271∶119847.96/4852.82560108037501100Low
1142160p4816∶91∶159447.96/481083840216055002250Low
1152160p48256∶1351∶159447.96/481084096216055002250Low
1162160p4864∶274∶359447.96/481083840216055002250Low
1172160p10016∶91∶11188100225.03840216052802250100
1182160p12016∶91∶11188119.88/120270.03840216044002250120
1192160p10064∶274∶31188100225.03840216052802250100
1202160p12064∶274∶31188119.88/120270.03840216044002250120
1212160p2x2464∶271∶139623.98/2452.85120216075002200Low
1222160p2x2564∶271∶13962555.05120216072002200Low
1232160p2x3064∶271∶139629.97/3066.05120216060002200Low
1242160p2x4864∶271∶1742.547.96/48118.85120216062502450Low
1252160p2x5064∶271∶1742.550112.5512021606600225050
1262160p2x64∶271∶1742.560135.0512021605500225060
1272160p2x10064∶271∶11485100225.05120216066002250100
128—192reserved, value range is used in SVD to indicate native timing for numbers 1—64.
1932160p2x12064∶271∶11485.0119.88/1202705120216055002250120
1944320p2416∶91∶11188.023.98/2410876804320110004500Low
1954320p2516∶91∶11188.02511076804320108004400Low
1964320p3016∶91∶11188.029.97/301327680432090004400Low
1974320p4816∶91∶12376.047.96/4821676804320110004500Low
1984320p5016∶91∶12376.0502207680432010800440050
1994320p16∶91∶12376.060264768043209000440060
2004320p10016∶91∶14752.010045076804320105604500100
2014320p12016∶91∶14752.0119.88/1205407680432088004500120
2024320p2464∶274∶31188.023.98/2410876804320110004500Low
2034320p2564∶274∶31188.02511076804320108004400Low
2044320p3064∶274∶31188.029.97/301327680432090004400Low
2054320p4864∶274∶32376.047.96/4821676804320110004500Low
2064320p5064∶274∶32376.0502207680432010800440050
2074320p64∶274∶32376.060264768043209000440060
2084320p10064∶274∶34752.010045076804320105604500100
2094320p12064∶274∶34752.0119.88/1205407680432088004500120
2104320p2x2464∶271∶11485.023.98/24118.8102404320125004950Low
2114320p2x2564∶271∶11485.025110102404320135004400Low
2124320p2x3064∶271∶11485.029.97/30135102404320110004500Low
2134320p2x4864∶271∶12970.047.96/48237.6102404320125004950Low
2144320p2x5064∶271∶12970.05022010240432013500440050
2154320p2x64∶271∶12970.06027010240432011000440060
2164320p2x10064∶271∶15940.0100450102404320132004500100
2174320p2x12064∶271∶15940.0119.88/120540102404320110004500120
2182160p100256∶1351∶11188.01002254096216052802250100
2192160p120256∶1351∶11188.0119.88/1202704096216044002250120

Notes: Parentheses indicate instances where pixels are repeated to meet the minimum speed requirements of the interface. For example, in the 720x240p case, the pixels on each line are double-clocked. In the (2880)x480i case, the number of pixels on each line, and thus the number of times that they are repeated, is variable, and is sent to the DTV monitor by the source device.

Increased Hactive expressions include “2x” and “4x” indicate two and four times the reference resolution, respectively.

Video modes with vertical refresh frequency being a multiple of 6 Hz (i.e. 24, 30, 60, 120, and 240 Hz) are considered to be the same timing as equivalent NTSC modes where vertical refresh is adjusted by a factor of 1000/1001. As VESA DMT specifies 0.5% pixel clock tolerance, which 5 times more than the required change, pixel clocks can be adjusted to maintain NTSC compatibility; typically, 240p, 480p, and 480i modes are adjusted, while 576p, 576i and HDTV formats are not.

A Vendor Specific Data Block (if any) contains as its first three bytes the vendor's IEEE 24-bit registration number, [23] least significant byte first. The remainder of the Vendor Specific Data Block is the "data payload", which can be anything the vendor considers worthy of inclusion in this EDID extension block. For example, IEEE registration number 00 0C 03 means this is a "HDMI Licensing, LLC" specific data block (contains HDMI 1.4 info), C4-5D-D8 means this is a "HDMI Forum" specific data block (contains HDMI 2.0 info), 00 D0 46 means this is "DOLBY LABORATORIES, INC." (contains Dolby Vision info) and 90 84 8b is "HDR10+ Technologies, LLC" (contains HDR10+ info as part of HDMI 2.1 Amendment A1 standard [24] ). It starts with a two byte source physical address, least significant byte first. The source physical address provides the CEC physical address for upstream CEC devices. HDMI 1.3a specifies some requirements for the data payload.

Vendor Specific Data Block for "HDMI Licensing LLC"
ByteDescription
0Data block header
1–3IEEE Registration Identifier (little endian)
4–5Components of Source Physical Address [25]
6(optional) 1, supported; 0, unsupported:
Bit 7A function that needs info from ACP or ISRC packets
Bit 616-bit-per-channel deep color (48-bit)
Bit 512-bit-per-channel deep color (36-bit)
Bit 410-bit-per-channel deep color (30-bit)
Bit 34∶4∶4 in deep color modes
Bit 2Reserved, 0
Bit 1Reserved, 0
Bit 0DVI Dual Link Operation
7(optional) Maximum TMDS frequency. 0, unspecified; else, Max_TMDS_Frequency / 5 MHz
8(optional) Latency fields indicators 1, present; 0, absent:
Bit 7Latency fields
Bit 6Interlaced latency fields. Absent if latency fields are absent.
Bits 5–0Reserved, 0
9Video latencyoptional; if indicated, value = 1 + ms/2 with a max. of 251 meaning 500 ms
10Audio latency
(video delay for progressive sources)
11Interlaced video latency
12Interlaced audio latency
(video delay for interlaced sources)
13+Additional bytes may be present, but the HDMI spec. says they shall be 00.

If a Speaker Allocation Data Block is present, it will consist of three bytes. The first and second bytes contain information about which speakers (or speaker pairs) are present in the display device:

Speaker Allocation Data Block
ByteDescription
0Data block header
11, present; 0, absent:
Bit 7Front left/right wide (FLw/FRw)
Bit 6Rear left/right center (RLC/RRC)
Bit 5Front left/right center (FLc/FRc)
Bit 4Back center (BC)
Bit 3Back left/right (BL/BR)
Bit 2Front center (FC)
Bit 1Low-frequency effects (LFE)
Bit 0Front left/right (FL/FR)
2
Bits 7-3Reserved, 0
Bit 2Top front center (TpFC)
Bit 1Top center (TpC)
Bit 0Top front left/right (TpFL/TpFR)
3Reserved, 00

The Room Configuration Data Block and Speaker Location Data Blocks describe the speaker setup using room coordinates. If sources can decode these blocks, they should ignore data in the Speaker Allocation Data block above.

Room Configuration Data Block
ByteDescription
0Data block header
Bits 7-5111=7, block type tag
Bits 4-0Length of payload data that follows this block, in bytes
113 = extended tag code
3Configuration
Bit 7Display data is valid
Bit 6Speaker count is valid
Bit 5Speaker location descriptors (SLD) are present
Bits 4-0Speaker count (1-32)
4Speaker presence mask 1 (SPM1): 1, present; 0, absent
Bit 7Front left/right wide (FLw/FRw)
Bit 6Rear left/right center (RLC/RRC)
Bit 5Front left/right center (FLc/FRc)
Bit 4Back center (BC)
Bit 3Back left/right (BL/BR)
Bit 2Front center (FC)
Bit 1Low-frequency effects 1 (LFE1)
Bit 0Front left/right (FL/FR)
5Speaker presence mask 2 (SPM2): 1, present; 0, absent
Bit 7Top side left/right (TpSiL/TpSiR)
Bit 6Side left/right (SiL/SiR)
Bit 5Top back center (TpBC)
Bit 4Low-frequency effects 2 (LFE2)
Bit 3Left/right surround (LS/RS)
Bit 2Top front center (TpFC)
Bit 1Top center (TpC)
Bit 0Top front left/right (TpFL/TpFR)
6Speaker presence mask 3 (SPM3): 1, present; 0, absent
Bits 7-4Reserved, 0
Bit 3Top left/right surround (TpLS/TpRS)
Bit 2Bottom front left/right (BtFL/BtFR)
Bit 1Bottom front center (BtFC)
Bit 0Top back left/right (TpBL/TpBR)
7-9Maximum distance from the primary listening position to the farthest speakers along X, Y, Z axes, if speaker location descriptors (SLD) blocks are present; otherwise 00 = undefined
10-13Distance from the primary listening position to the center of display along X, Y, Z axes; 00 = undefined when display data flag is not set

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References

  1. ↑ "High-Definition Multimedia Interface Specification Version 1.3a" (PDF). 10 November 2006. Archived from the original (PDF) on 5 March 2016. Retrieved 2017-04-01.
  2. ↑ "read-edid". Polypux.org. Archived from the original on 2010-12-11. Retrieved 2017-04-01.
  3. ↑ "Utilities | PowerStrip". EnTech Taiwan. 2012-03-25. Archived from the original on 2011-03-08. Retrieved 2017-04-01.
  4. ↑ "SwitchResX - The Most Versatile Tool For Controlling Screen Resolutions On Your Mac". Madrau.com. Archived from the original on 2009-02-08. Retrieved 2017-04-01.
  5. ↑ Harald Schweder (2003-02-11). "DisplayConfigX". 3dexpress.de. Archived from the original on 2011-07-18. Retrieved 2017-04-01.
  6. ↑ "VESA Display Device Data Block (DDDB) Standard" (PDF). github.io. 25 September 2006. Archived (PDF) from the original on 2021-04-17.
  7. ↑ Brezenski (2009-08-07). "Custom Resolutions on Intel Graphics". Software.intel.com. Archived from the original on 2011-03-15. Retrieved 2009-11-04.
  8. 1 2 3 4 5 6 7 8 9 10 VESA E-EDID Standard, Release A, Revision 2. September 25, 2006 Archived November 11, 2020, at the Wayback Machine ;
  9. ↑ VESA Enhanced EDID Standard (PDF), Video Electronics Standards Association, 2000-02-09, p. 32, archived (PDF) from the original on 2012-04-25, retrieved 2011-11-19
  10. ↑ "CTA-861 – CTA's Most Popular Standard". Consumer Technology Association®. CTA. Archived from the original on 11 October 2022.
  11. ↑ "A DTV Profile for Uncompressed High Speed Digital Interfaces (CTA-861-E)". Consumer Technology Association®. CTA. Retrieved 4 August 2023.
  12. ↑ "A DTV Profile for Uncompressed High Speed Digital Interfaces (CTA-861-F)". Consumer Technology Association®. CTA. Retrieved 4 August 2023.
  13. ↑ "A DTV Profile for Uncompressed High Speed Digital Interfaces (ANSI/CTA-861-H)". Consumer Technology Association®. CTA. Retrieved 4 August 2023.
  14. ↑ "A DTV Profile for Uncompressed High Speed Digital Interfaces (ANSI/CTA-861-I)". Consumer Technology Association®. CTA. Retrieved 4 August 2023.
  15. ↑ Paul Ploumis (2013-07-16). "CEA publishes new high-speed CEA-861-F DTV Interface Standard". Scrapmonster.com. Archived from the original on 2017-04-15. Retrieved 2017-04-01.
  16. ↑ "A DTV Profile for Uncompressed High Speed Digital Interfaces" (PDF). 29 November 2017. CTA-861-G. Archived from the original (PDF) on 2017-11-30. Retrieved 2017-11-30.
  17. ↑ "CTA's Entire Library of Industry Standards Now Free to Everyone". www.cta.tech. Archived from the original on 29 July 2019. Retrieved 2 April 2020.
  18. ↑ "News - "Confidential" HDMI Specifications Docs Hit With DMCA Takedown". TV ADDONS. Archived from the original on 18 September 2020. Retrieved 2 April 2020.
  19. ↑ "A DTV Profile for Uncompressed High Speed Digital Interfaces (ANSI/CTA-861-I)". Consumer Technology Association®. Archived from the original on 29 March 2023. Retrieved 29 March 2023.
  20. ↑ "A DTV Profile for Uncompressed High Speed Digital Interfaces (ANSI/CTA-861-H)". 27 May 2021. CTA-861-H. Archived from the original on 2021-06-21. Retrieved 2021-05-27.
  21. ↑ "Improvements on Audio and Video Signaling (CTA-861.6)". 2022-03-14. CTA-861.6. Archived from the original on 2022-05-17. Retrieved 2022-06-24.
  22. ↑ "OVT - Optimized Video Timing Generator - CTA". www.cta.tech. CTA. Retrieved 4 August 2023.
  23. ↑ "Welcome to The Public Listing For IEEE Standards Registration Authority". regauth.standards.ieee.org. Archived from the original on 13 May 2020. Retrieved 1 April 2020.
  24. ↑ "edid-decode.git - edid-decode main repository". git.linuxtv.org. Archived from the original on 1 August 2020. Retrieved 2 April 2020.
  25. ↑ see section 8.7 of HDMI 1.3a
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