Intel 5 Series

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Intel 5 Series is a computing architecture introduced in 2008 that improves the efficiency and balances the use of communication channels in the motherboard. The architecture consists primarily of a central processing unit (CPU) (connected to the graphics card and memory) and a single chipset (connected to motherboard components). All motherboard communications and activities circle around these two devices.

Contents

The architecture is a product of adjustments made to the Intel 4 Series to deliver higher performance motherboards while maintaining efficiency and low power. The changes revolve around chipset and processor design, in conjunction with a rearrangement of functions and controllers. The result is the first major change in many years of computing.

Design concept

Intel 4 Series Motherboard Design Intel 4 Series arch.png
Intel 4 Series Motherboard Design

The concept of the architecture was to improve motherboard mechanics to keep pace with the CPU as it gained more speed and multiplied in number of cores. In the previous architecture, the CPU was communicating heavily with the motherboard's central component, the Northbridge chipset, as it was the intermediary between the CPU, memory, and, in most cases, graphics card. The CPU would communicate with the Northbridge chipset when it needed data from the memory or when it needed to output graphics to the display. This arrangement caused the communication channel known as the front-side bus (FSB) to be heavily used. It was not long till either the FSB would reach full capacity or operate inefficiently with more cores. With the memory controller and/or graphics core moved into the processor, the reliance of separate motherboard chipsets for these functions are reduced.

Ibex Peak

Intel 5 Series (Ibex Peak) Motherboard Solution Intel 5 Series architecture.png
Intel 5 Series (Ibex Peak) Motherboard Solution

The Ibex Peak chipset includes only Platform Controller Hub (PCH) per model, which provides peripheral connections, and display controllers for CPU with integrated graphics via Flexible Display Interface (excluding P-models). Additionally, the PCH is connected to the CPU via Direct Media Interface (DMI).

Taking advantage of Nehalem CPUs with integrated graphics and PCI Express ports, the Intel Management Engine (ME) and a display controller for integrated graphics, once housed in north bridge, are moved into the Platform Controller Hub (PCH). The I/O Controller Hub (ICH) function is integrated into the PCH, removing the need for separate north bridge and south bridge.

Intel 5 Series Ibex Peak
ChipsetCode NamesSpec NumberPart numbersRelease DateBus InterfaceLink Speed [lower-alpha 1] PCI Express lanes PCI SATA USB FDI support TDP
3 Gbit/sv2.0
H55 Ibex Peak [1] [2] SLGZX(B3)BD82H55 (PCH)Jan 2010 DMI 2 GB/s6 PCIe 2.0 at 2.5 GT/sYes6 ports12 portsYes5.2 W
P55 SLH24 (B3),
SLGWV (B2)
BD82P55 (PCH)Sep 20098 PCIe 2.0 at 2.5 GT/s14 portsNo4.7 W
H57 SLGZL(B3)BD82H57 (PCH)Jan 2010Yes5.2 W
Q57 SLGZW(B3)BD82Q57 (PCH)5.1 W
Mobile Intel 5 Series
ModelTop marking
PM55 ExpressBD82PM55
QM57 ExpressBD82QM57
HM55 ExpressBD82HM55
HM57 ExpressBD82HM57
QS57 ExpressBD82QS57
Intel 3400 Series
ModelTop markingFab ME Firmware Version PCIe
3400 BD340065 nm6.02.0
3420 BD3420
3450 BD3450

Tylersburg

The Tylersburg family of chipsets is for Socket LGA 1366 supporting CPUs with triple channel memory controllers. Unlike the Ibex Peak chipsets, The Tylersburg family of chipsets do not include the PCH, and the I/O Hub mainly provides extra PCI Express 2.0 ports. Peripheral connections are provided by I/O Controller Hub (ICH) connected to the DMI interface. Intel 5 series IOH support ICH10, while Intel 5500 Series IOH support ICH9 or ICH10.

Single socket Nehalem-based chipset

Intel 5 Series
ChipsetCode NamesSpec NumberPart numbersRelease DateSocketBus Interface PCI Express lanes PCI Intel VT-d support SATA USB FDI support TDP
6 Gbit/s3 Gbit/sv3.0v2.0
X58 1TylersburgSLGBT (B2),
SLGMX (B3),
SLH3M (C2)
AC82X58 (IOH)November 2008 LGA 1366 QPI 36× PCIe 2.0 (IOH);
6× PCIe 1.1 (ICH)
YesYesNone6 portsNone12 portsNo28.6 W2

Dual socket Nehalem-based Xeon chipsets

The Nehalem-based Xeons for dual-socket systems, initially launched as the Xeon 55xx series, feature a very different system structure: the memory controllers are on the CPU, and the CPUs can communicate with one another as peers without going via the chipset. This means that the 5500 and 5520 (initial codename Tylersburg-EP) chipsets are essentially QPI to PCI Express interfaces; the 5520 is more intended for graphical workstations and the 5500 for servers that do not need vast amounts of PCI Express connectivity

Xeon 5500 series
Launch nameCodenameQPI portsQPI speedFast I/OIOCHOther featuresTop marking
5500 Tylersburg-24S,
Tylersburg-24D [3]
1,
2
4.8, 5.86 or 6.4 GT/s1 ×16 PCIe Gen 2, 2 ×4 PCIe Gen 1 to talk to southbridgeICH10 (ICH9 also possible)Integrated Management Engine with its own 100 Mbit Ethernet [4] AC5500 SLGMT 901036 (B-3), AC5500 SLH3N 904728 (C-2)
5520 Tylersburg-36S,
Tylersburg-36D
1,
2
4.8, 5.86 or 6.4 GT/s2 ×16 PCIe Gen 2, 1 ×4 PCIe Gen 1 to talk to southbridgeICH10 (ICH9 also possible)Integrated Management Engine with its own 100 Mbit Ethernet [4] AC5520 SLGMU 901037 (B-3), AC5520 SLH3P 904729 (C-2)

See also

Notes

Related Research Articles

<span class="mw-page-title-main">Front-side bus</span> Type of computer communication interface

The front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the central processing unit (CPU) and a memory controller hub, known as the northbridge.

<span class="mw-page-title-main">Xeon</span> Line of Intel server and workstation processors

Xeon is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded markets. It was introduced in June 1998. Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support for error correction code (ECC) memory, higher core counts, more PCI Express lanes, support for larger amounts of RAM, larger cache memory and extra provision for enterprise-grade reliability, availability and serviceability (RAS) features responsible for handling hardware exceptions through the Machine Check Architecture (MCA). They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the machine-check exception (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the Ultra Path Interconnect (UPI) bus, which replaced the older QuickPath Interconnect (QPI) bus.

<span class="mw-page-title-main">Chipset</span> Electronic component to manage data flow of a CPU

In a computer system, a chipset is a set of electronic components on one or more integrated circuits that manages the data flow between the processor, memory and peripherals. The chipset is usually found on the motherboard of computers. Chipsets are usually designed to work with a specific family of microprocessors. Because it controls communications between the processor and external devices, the chipset plays a crucial role in determining system performance.

<span class="mw-page-title-main">Northbridge (computing)</span> PC chip handling onboard control tasks

In computing, a northbridge is a microchip that comprises the core logic chipset architecture on motherboards to handle high-performance tasks, especially for older personal computers. It is connected directly to a CPU via the front-side bus (FSB), and is usually used in conjunction with a slower southbridge to manage communication between the CPU and other parts of the motherboard.

<span class="mw-page-title-main">Southbridge (computing)</span> One of the two chips in the core logic chipset architecture on a PC motherboard

On older personal computer motherboards, the southbridge is one of the two chips in the core logic chipset, handling many of a computer's input/output functions. The other component of the chipset is the northbridge, which generally handles onboard control tasks.

The Intel QuickPath Interconnect (QPI) is a point-to-point processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and available bandwidth. Prior to the name's announcement, Intel referred to it as Common System Interface (CSI). Earlier incarnations were known as Yet Another Protocol (YAP) and YAP+.

Intel Hub Architecture (IHA), also known as Accelerated Hub Architecture (AHA) was Intel's architecture for the 8xx family of chipsets, starting in 1999 with the Intel 810. It uses a memory controller hub (MCH) that is connected to an I/O controller hub (ICH) via a 266 MB/s bus. The MCH chip supports memory and AGP, while the ICH chip provides connectivity for PCI, USB, sound, IDE hard disks and LAN.

<span class="mw-page-title-main">Nehalem (microarchitecture)</span> CPU microarchitecture by Intel

Nehalem is the codename for Intel's 45 nm microarchitecture released in November 2008. It was used in the first generation of the Intel Core i5 and i7 processors, and succeeds the older Core microarchitecture used on Core 2 processors. The term "Nehalem" comes from the Nehalem River.

<span class="mw-page-title-main">Sandy Bridge</span> Intel processor microarchitecture

Sandy Bridge is the codename for Intel's 32 nm microarchitecture used in the second generation of the Intel Core processors. The Sandy Bridge microarchitecture is the successor to Nehalem and Westmere microarchitecture. Intel demonstrated an A1 stepping Sandy Bridge processor in 2009 during Intel Developer Forum (IDF), and released first products based on the architecture in January 2011 under the Core brand.

<span class="mw-page-title-main">Direct Media Interface</span> Intel bus for connecting CPU and I/O chipset

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I/O Controller Hub (ICH) is a family of Intel southbridge microchips used to manage data communications between a CPU and a motherboard, specifically Intel chipsets based on the Intel Hub Architecture. It is designed to be paired with a second support chip known as a northbridge. As with any other southbridge, the ICH is used to connect and control peripheral devices.

<span class="mw-page-title-main">Intel X58</span> Chip designed by Intel

The Intel X58 is an Intel chip designed to connect Intel processors with Intel QuickPath Interconnect (QPI) interface to peripheral devices. Supported processors implement the Nehalem microarchitecture and therefore have an integrated memory controller (IMC), so the X58 does not have a memory interface. Initially supported processors were the Core i7, but the chip also supported Nehalem and Westmere-based Xeon processors.

<span class="mw-page-title-main">Platform Controller Hub</span> Family of Intels single-chip chipsets

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<span class="mw-page-title-main">LGA 1366</span> CPU socket for Intel processors

LGA 1366, also known as Socket B, is an Intel CPU socket. This socket supersedes Intel's LGA 775 in the high-end and performance desktop segments. It also replaces the server-oriented LGA 771 in the entry level and is superseded itself by LGA 2011. This socket has 1,366 protruding pins which touch contact points on the underside of the processor (CPU) and accesses up to three channels of DDR3 memory via the processor's internal memory controller.

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The Intel X79 is a Platform Controller Hub (PCH) designed and manufactured by Intel for their LGA 2011 and LGA 2011-1.

Intel X99, codenamed "Wellsburg", is a Platform Controller Hub (PCH) designed and manufactured by Intel, targeted at the high-end desktop (HEDT) and enthusiast segments of the Intel product lineup. The X99 chipset supports both Intel Core i7 Extreme and Intel Xeon E5-16xx v3 and E5-26xx v3 processors, which belong to the Haswell-E and Haswell-EP variants of the Haswell microarchitecture, respectively. All supported processors use the LGA 2011-v3 socket.

Raptor Lake is Intel's codename for the 13th and 14th generations of Intel Core processors based on a hybrid architecture, utilizing Raptor Cove performance cores and Gracemont efficient cores. Like Alder Lake, Raptor Lake is fabricated using Intel's Intel 7 process. Raptor Lake features up to 24 cores and 32 threads and is socket compatible with Alder Lake systems. Like earlier generations, Raptor Lake processors also need accompanying chipsets.

References

  1. Intel 5 Series Chipset
  2. Mobile Intel 5 Series Chipset
  3. "Intel X58 Extreme DX58SO motherboard review". Guru3D.com. Retrieved 30 April 2023.
  4. 1 2 "Intel® 5520 Chipset and Intel® 5500 Chipset" (PDF). intel.com. March 2009. Retrieved 30 April 2023.

Ibex Peak

Tylersburg