List of VIA microprocessor cores

Last updated

This article lists x86-compliant microprocessors sold by VIA Technologies, grouped by technical merits: cores within same group have much in common.

Contents

Cyrix design (Cyrix III)

Marketing
name		CoreFrequency Front-side bus L1-cache L2-cache FPU
speed		Pipeline
stages		Typical powerVoltageProcess
Cyrix IIIJoshua350-450 MHz100-133 MHz64 KB 256 KB100% ?13-16 W2.2 V180 nm Al

Centaur Technology design

Cyrix III, C3

Marketing
name		CoreFrequencyFront-side busL1 cacheL2 cacheFPU
speed		Pipeline
stages		Typical powerVoltageProcess
Cyrix III, C3, 1GigaProSamuel (C5A)466-733 MHz100-133 MHz128 KB0 KB50%126.8-10.6 W1.8-2.0 V180 nm Al
Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+Samuel 2 (C5B)600-800 MHz100-133 MHz128 KB64 KB50%125.8-6.6 W1.5-1.65 V150 nm Al
C3, Eden ESPEzra (C5C)733-933 MHz100-133 MHz128 KB64 KB50%125.3-5.9 W1.35 V130 nm Al
C3Ezra-T (C5N)800-1000 MHz100-133 MHz128 KB64 KB50%125.3-11.8 W1.35 V130 nm Al

C3, C7

Marketing
name		CoreFrequencyFront-side busL1 cacheL2 cacheFPU
speed		Pipeline
stages		Typical powerVoltageProcess
C3, Eden ESP, Eden-NNehemiah (C5XL)800-1400 MHz133 MHz128 KB64 KB100%1615-19 W1.25 or 1.4-1.45 V130 nm Cu
C3Nehemiah+ (C5P)1-1.4 GHz133 MHz128 KB64 KB100%1611-12 W1.25 V130 nm Cu
C7, C7-D, C7-M, Eden, Eden ULVEsther (C5J)0.4-2.0 GHz400-533 MT/s128 KB128 KB100%1612-20 W0.9-1.1(?) V90 nm SOI
SeriesModelCoreFrequency
[MHz]		 Front-side bus
[MHz]		YearProcess
[nm]		Package size
[mm2]		Power
[W]		L2 cache
[K]		L1 I/D cache
[K]		Performance
[SPEC2000]
Eden Eden ESPSamuel 2300–60066/100/133200115035×352.5–66464/64Un­known
Eden ESPNehemiah667–1000133/2002003–200413035×356–76464/64Un­known
Eden-NNehemiah533–1000133200313015×152.5–76464/64Un­known
EdenEsther400–1500400–8002006–20079030<7.512832/32Un­known
Eden X2Un­known800Un­known20114011×6Un­knownUn­knownUn­knownUn­known
C3 C3Samuel 2667–800100–1332001150Un­known136464/64Un­known
C3Ezra800–1000100–1332002130Un­known8.3–106464/64Un­known
C3Nehemiah1000–1400133–200200313035×3515–216464/64Un­known
C3-MNehemiah1000–1400133–200200313035×3511–196464/64Un­known
C7 C7-DEsther1500–180040020069021×2120–2512816/16Un­known
C7-MEsther1000–200040020059021×2112–2012816/16Un­known
C7Esther1500–200080020079021×2112–2012816/16Un­known

Nano

SeriesModelCoreFrequency
[MHz]		 Front-side bus
[MHz]		YearProcess
[nm]		Package size
[mm2]		Power
[W]		L2 cache
[K]		L1 I/D cache
[K]		Performance
[SPEC2000]
QuadCore QuadCoreIsaiah1000-1460106620114021×2127.54× 1024 [5] 4× 64/6430.1/24.1 rate [6]

CHA

Marketing
name		Code nameCoreNumber of coresFrequencyMicroarchitectureL1 cacheL2 cacheL3 cacheAnnouncedExpected ReleaseProcessSocket TypePipeline stagesPCIe Lanes
unknownCHACNS82.5 GHzCNS [11] 32 KiB256 KiB16 MB20192H 2020 [12] 16 nmLGA20-2244 [13]

See also

Related Research Articles

In computing, Streaming SIMD Extensions (SSE) is a single instruction, multiple data (SIMD) instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of central processing units (CPUs) shortly after the appearance of Advanced Micro Devices (AMD's) 3DNow!. SSE contains 70 new instructions, most of which work on single precision floating-point data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are digital signal processing and graphics processing.

Visual Instruction Set, or VIS, is a SIMD instruction set extension for SPARC V9 microprocessors developed by Sun Microsystems. There are five versions of VIS: VIS 1, VIS 2, VIS 2+, VIS 3 and VIS 4.

SSE2 is one of the Intel SIMD processor supplementary instruction sets introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier SSE instruction set, and is intended to fully replace MMX. Intel extended SSE2 to create SSE3 in 2004. SSE2 added 144 new instructions to SSE, which has 70 instructions. Competing chip-maker AMD added support for SSE2 with the introduction of their Opteron and Athlon 64 ranges of AMD64 64-bit CPUs in 2003.

SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. In April 2005, AMD introduced a subset of SSE3 in revision E of their Athlon 64 CPUs. The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow!, SSE, and SSE2.

<span class="mw-page-title-main">VIA C7</span> Central processing unit designed by Centaur Technology and sold by VIA Technologies

The VIA C7 is an x86 central processing unit designed by Centaur Technology and sold by VIA Technologies.

The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. The first third-generation Opteron products for servers were launched on September 10, 2007, with the Phenom processors for desktops following and launching on November 11, 2007 as the immediate successors to the K8 series of processors.

<span class="mw-page-title-main">VIA Nano</span>

The VIA Nano is a 64-bit CPU for personal computers. The VIA Nano was released by VIA Technologies in 2008 after five years of development by its CPU division, Centaur Technology. This new Isaiah 64-bit architecture was designed from scratch, unveiled on 24 January 2008, and launched on 29 May, including low-voltage variants and the Nano brand name. The processor supports a number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances.

References

  1. ↑ "IA-32 implementation: VIA Cyrix III". sandpile.org. Archived from the original on 2007-07-09. Retrieved 2007-07-23.
  2. ↑ "IA-32 implementation: VIA C3". sandpile.org. Archived from the original on 2007-07-17. Retrieved 2007-07-23.
  3. ↑ "IA-32 implementation: VIA C7". sandpile.org. Archived from the original on 2007-06-30. Retrieved 2007-07-23.
  4. "VIA Nano X2 SPEC2000 ratio and rate scores". Via.com. Archived from the original on 7 February 2014. Retrieved 3 February 2014.
  5. ↑ "VIA QuadCore Processor". Via.com. Retrieved 2014-02-03.
  6. ↑ "VIA Nano X2 Whitepaper" (PDF). Via.com. Archived from the original (PDF) on 27 May 2012. Retrieved 3 February 2014.
  7. ↑ "VIA CenTaur Develops a Multi-core x86 Processor for Enterprise with in-built AI Hardware". TechPowerUp. November 18, 2019h. Retrieved 2020-07-28.
  8. ↑ "VIA CenTaur CHA NCORE AI CPU Pictured, a Socketed LGA Package". TechPowerUp. February 18, 2020. Retrieved 2020-07-28.
  9. ↑ "CHA - Microarchitectures - Centaur Technology - WikiChip". en.wikichip.org. Retrieved 2020-07-28.
  10. ↑ "The Last x86 Via Chip: Unreleased Next-Gen Centaur CNS Saved From Trash Bin, Tested". TomsHardware. 22 February 2022.
  11. ↑ "VIA x86 AI processor architecture, performance announcement: comparable to Intel 32 core". Small Tech News. December 11, 2019.
  12. ↑ "Centaur Releases In-Depth Analysis from The Linley Group for its NCORE-Equipped x86 Processor". TechPowerUp. December 9, 2019. Retrieved 2020-08-30.
  13. ↑ "World's First High-Performancex86 SoCwithIntegrated AI Coprocessor" (PDF). centtech. p. 4. Archived from the original on November 19, 2019.{{cite web}}: CS1 maint: unfit URL (link)
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