General information | |
---|---|
Launched | 1975 |
Common manufacturer | |
Performance | |
Max. CPU clock rate | to 3.3 MHz |
Data width | 8 (microdata), 18 (microcode), 16 (macrodata) |
Address width | 11 (microcode), 16 (macrodata) |
Architecture and classification | |
Number of instructions | 98 |
Physical specifications | |
Package |
|
History | |
Successor | none |
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | (bit position) |
Register file | LSI-11 use [1] | |||||||||||||||
R3 | R2 | PSW | ||||||||||||||
R5 | R4 | Destination | ||||||||||||||
R7 | R6 | Source | ||||||||||||||
R9 | R8 | Bus address | ||||||||||||||
RB | RA | Instruction register | ||||||||||||||
RD/GD | RC/GC | R7 (PC) | ||||||||||||||
RF/GF | RE/GE | R6 (SP) | ||||||||||||||
GB | GA | R5 | ||||||||||||||
G9 | G8 | R4 | ||||||||||||||
G7 | G6 | R3 | ||||||||||||||
G5 | G4 | R2 | ||||||||||||||
G3 | G2 | R1 | ||||||||||||||
G1 | G0 | R0 | ||||||||||||||
Control registers | ||||||||||||||||
G | Register Pointer | |||||||||||||||
LC | Location Counter | |||||||||||||||
RR | Return Register | |||||||||||||||
TR1 | TR0 | Translation Register | ||||||||||||||
Status register | ||||||||||||||||
NB | ZB | C4 | C8 | N | Z | V | C | ALU status/Flags |
The MCP-1600 is a multi-chip 16-bit microprocessor introduced by Western Digital in 1975 and produced through the early 1980s. [2] [3] Used in the Pascal MicroEngine, the WD16 processor in the Alpha Microsystems AM-100, and the DEC LSI-11 microcomputer, [4] a cost-reduced and compact implementation of the DEC PDP-11.
There are three types of chips in the chip-set:
The chips use a 3.3MHz four phase clock and three power supply voltages (+5V, +12V, and -5V), as required by the N-channel silicon gate process then available at Western Digital. Internally the MCP-1600 is a (relatively fast) 8-bit processor that can be micro-programmed to emulate a 16-bit CPU. All byte operations execute in one clock period; word operations and branches take two clocks. Up to four MICROMs are supported, but usually two or three could hold the needed microprogram for a processor. [5]
The register file consists of 26 8-bit registers. Ten may be addressed directly by the microinstruction (Rx), four may be addressed either directly or indirectly (Rx/Gx), and the remaining 12 may be addressed only indirectly (Gx). Indirect addressing is via a 3-bit G register which is usually loaded with the register field of the PDP-11 instruction. [1]
The most significant feature of the MCP-1600 is its Programmable Translation Array (PTA). The PTA serves to generate new microinstruction fetch addresses as a function of several parameters. These parameters are those which are normally considered during the decode of a macroinstruction. The PTA was designed specifically to eliminate most of the overhead of macroinstruction translation. Essentially a macroinstruction opcode is quickly translated into an address that is loaded onto the Location Counter, creating a jump to the appropriate microcode to handle the macroinstruction. [5]
John Wallace was the Project Manager and designed the 1621, Mike Briner designed the 1611, and later became a Senior VP at Silicon Storage Technology. Bill Pohlman was the design engineering manager and he later was Project Manager for the Intel 8086 processor.
Microcode could be developed using a DEC LSI-11 computer with the KUV11-AA Writable Control Store (WCS) option. This option allowed programming of the internal 8-bit micromachine to create application-specific extensions to the instruction set. The WCS is a quad Q-Bus board with a ribbon cable connecting to an open MCP-1600 microcode ROM socket. [6]
In March 1976, it was announced that National Semiconductor would second-source the MCP-1600. It is unclear whether any were produced by National. [7]
A clone of the CP1611 and CP1621 was manufactured in the Soviet Union under the designation KR581IK1 and KR581IK2 (Russian : КР581ИК1 and КР581ИК2). [8] The Soviet 581 series included other members of the MCP-1600 family as well. [9]
cp16sim is an open source MCP-1600 simulator. Written in C, it emulates the MCP-1600 processor and its PTA executing the code found on the WD9000 Pascal Microengine processor. As of 2016 it is unfinished. "It works well enough to execute the first few dozen p-code instructions of the ACD PDQ-3 boot ROM before going into the weeds." It is released under the GNU General Public License version 3. [10]
A control store is the part of a CPU's control unit that stores the CPU's microprogram. It is usually accessed by a microsequencer. A control store implementation whose contents are unalterable is known as a Read Only Memory (ROM) or Read Only Storage (ROS); one whose contents are alterable is known as a Writable Control Store (WCS).
In processor design, microcode serves as an intermediary layer situated between the central processing unit (CPU) hardware and the programmer-visible instruction set architecture of a computer, also known as its machine code. It consists of a set of hardware-level instructions that implement the higher-level machine code instructions or control internal finite-state machine sequencing in many digital processing components. While microcode is utilized in general-purpose CPUs in contemporary desktops, it also functions as a fallback path for scenarios that the faster hardwired control unit is unable to manage.
The PDP–11 is a series of 16-bit minicomputers sold by Digital Equipment Corporation (DEC) from 1970 into the late 1990s, one of a set of products in the Programmed Data Processor (PDP) series. In total, around 600,000 PDP-11s of all models were sold, making it one of DEC's most successful product lines. The PDP-11 is considered by some experts to be the most popular minicomputer.
The Intel 4004 is a 4-bit central processing unit (CPU) released by Intel Corporation in 1971. Sold for US$60, it was the first commercially produced microprocessor, and the first in a long line of Intel CPUs.
In electronics and especially synchronous digital circuits, a clock signal is an electronic logic signal which oscillates between a high and a low state at a constant frequency and is used like a metronome to synchronize actions of digital circuits. In a synchronous logic circuit, the most common type of digital circuit, the clock signal is applied to all storage devices, flip-flops and latches, and causes them all to change state simultaneously, preventing race conditions.
The history of computing hardware starting at 1960 is marked by the conversion from vacuum tube to solid-state devices such as transistors and then integrated circuit (IC) chips. Around 1953 to 1959, discrete transistors started being considered sufficiently reliable and economical that they made further vacuum tube computers uncompetitive. Metal–oxide–semiconductor (MOS) large-scale integration (LSI) technology subsequently led to the development of semiconductor memory in the mid-to-late 1960s and then the microprocessor in the early 1970s. This led to primary computer memory moving away from magnetic-core memory devices to solid-state static and dynamic semiconductor memory, which greatly reduced the cost, size, and power consumption of computers. These advances led to the miniaturized personal computer (PC) in the 1970s, starting with home computers and desktop computers, followed by laptops and then mobile computers over the next several decades.
Bit slicing is a technique for constructing a processor from modules of processors of smaller bit width, for the purpose of increasing the word length; in theory to make an arbitrary n-bit central processing unit (CPU). Each of these component modules processes one bit field or "slice" of an operand. The grouped processing components would then have the capability to process the chosen full word-length of a given software design.
Pascal MicroEngine is a series of microcomputer products manufactured by Western Digital from 1979 through the mid-1980s, designed specifically to run the UCSD p-System efficiently. Compared to other microcomputers, which use a machine language p-code interpreter, the Pascal MicroEngine has its interpreter implemented in microcode; p-code is its machine language. The most common programming language used on the p-System is Pascal.
The CVAX is a microprocessor chipset developed and fabricated by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). The chipset consisted of the CVAX 78034 CPU, CFPA floating-point accelerator, CVAX clock chip, and the associated support chips, the CVAX System Support Chip (CSSC), CVAX Memory Controller (CMCTL), and CVAX Q-Bus Interface Chip (CQBIC).
The IMP-16, by National Semiconductor, was the first multi-chip 16-bit microprocessor, released in 1973. It consisted of five PMOS integrated circuits: four identical RALU chips, short for register and ALU, providing the data path, and one CROM, Control and ROM, providing control sequencing and microcode storage. The IMP-16 is a bit-slice processor; each RALU chip provides a 4-bit slice of the register and arithmetic that work in parallel to produce a 16-bit word length.
Joel McCormack is an American computer scientist who designed the NCR Corporation version of the p-code machine, which is a kind of stack machine popular in the 1970s as the preferred way to implement new computing architectures and languages such as Pascal and BCPL. The NCR design shares no common architecture with the Pascal MicroEngine designed by Western Digital but both were meant to execute the UCSD p-System.[1,2]
The V-11, code-named "Scorpio", is a miniprocessor chip set implementation of the VAX instruction set architecture (ISA) developed and fabricated by Digital Equipment Corporation (DEC).
The CP1600 is a 16-bit microprocessor created in a partnership between General Instrument and Honeywell, introduced in February 1975. It is one of the first single-chip 16-bit processors. The overall design bears a strong resemblance to the PDP-11.
The 1801 series CPUs were a family of 16-bit Soviet microprocessors based on the indigenous Elektronika NC microarchitecture cores, but binary compatible with DEC's PDP-11 machines. First released in 1980, various models and variants of the series were among the most popular Soviet microprocessors and dominated embedded systems and military applications of the 1980s. They were also used in widely different areas such as graphing calculators and industrial CNCs, but arguably their most well-known use was in several Soviet general-purpose mini- and microcomputer designs like the SM EVM, DVK, UKNC, and BK families. Due to being the CPU of the popular Elektronika BK home computer, used in its late years as a demo machine, as well as the DVK micros that often offered a first glimpse into the UNIX world, this processor achieved something of a cult status among Soviet and then Russian programmers, and to a lesser extent, international programmers.
In computer architecture, 16-bit integers, memory addresses, or other data units are those that are 16 bits wide. Also, 16-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers, address buses, or data buses of that size. 16-bit microcomputers are microcomputers that use 16-bit microprocessors.
Intel microcode is microcode that runs inside x86 processors made by Intel. Since the P6 microarchitecture introduced in the mid-1990s, the microcode programs can be patched by the operating system or BIOS firmware to work around bugs found in the CPU after release. Intel had originally designed microcode updates for processor debugging under its design for testing (DFT) initiative.
The Texas Instruments SBP0400, also known as SBC 0400 and X0400, is a microprogrammable 4-bit slice processor that was introduced in 1976. It was one of the first LSI processors and was the first device in the USA based on I²L technology. It was used for research and teaching purposes in the aerospace industry (NASA) and in the learning computer LCM-1001. This microprocessor learning computer was probably the company's first.
The Mostek MK5065 was an 8-bit microprocessor introduced by Mostek in early 1974. The design was originally developed by Motorola for use in an Olivetti electronic calculator, and was licensed to Mostek for use in non-calculator roles. It featured three sets of processor registers, allowing it to switch to an interrupt handler in a single cycle, and a wait-for-data mode that aided direct memory access.
The NCR/32 VLSI Processor family was a 32-bit microprocessor architecture and chipset developed by NCR Corporation in the early 1980s. Generally used in minicomputer systems, it was noteworthy for being externally microprogrammable.