Quantum Effect Devices (QED) was a microprocessor design company incorporated in 1991 as Quantum Effect Design. It was based in Palo Alto, California.
Quantum Effect Devices (QED) was a microprocessor design company incorporated in 1991 as Quantum Effect Design. It was based in Palo Alto, California.
The three founders, Tom Riordan, Earl Killian and Ray Kunita, were senior managers at MIPS Computer Systems Inc. They left MIPS at a time when the company was having a difficult time selling entire computer systems (MIPS Magnum) instead of concentrating on building microprocessor chips which was MIPS' original mission. Soon after, SGI purchased MIPS. IDT was a major funder and customer for the initial QED design.
The original product plan for QED was to build a MIPS microprocessor for a laptop computer. This was during the ACE initiative from Microsoft to support multiple RISC architectures for their new Windows NT operating system. System companies like DeskStation Technology and board companies like ShaBLAMM! Computer were building products in the hope that RISC-based personal computers would become mainstream. While that market never materialized, the first product, the R4600 "Orion" microprocessor, proved to be successful in several embedded markets such as networking routers and arcade games. Subsequent projects were designed for companies such as Toshiba and IDT (R4700), IDT & NKK (R4650), SGI and NEC (R5000).
The PowerPC 603q was a PowerPC microprocessor designed for Motorola, meant for Apple Computer's home PC and game machine designs. Neither of these designs were productized, so the PowerPC 603q never reached full production.
Several years later, in an attempt to increase product revenue, the company transformed itself to a product company selling its own line of MIPS microprocessors. At that time, the company changed its name to Quantum Effect Devices. After successful products introductions like the RM5200 and the RM7000, under its own "RISCMark" label, the company had its IPO on 1 February 2000. The initial stock price of $16 jumped to $56.50 on the first day of trading. [1] The company was acquired by PMC-Sierra on October 2000; at the time, Quantum Effect Devices was valued in a stock swap worth $2.3 billion according to one estimate. [2] The company became the Microprocessor Products Division of PMC. The acquisition was done by stock exchange and was valued at $2.3 billion. The team completed the RM9x00 product line while at PMC, but that product line was not successful in the marketplace. Most of the microprocessor core development team derived from QED was laid off as a group by PMC-Sierra in June 2005; the last few were laid off in January 2006.
The company name was attributed to Tom Riordan. He believed that the company would survive to the age when semiconductor geometry dimensions would become so small that quantum effects would dominate circuit behavior.
The first QED microprocessor was the R4600. The founders of QED, who were previously involved with the R4000, felt that the large device was too complicated and that a simpler implementation would give a better price/performance ratio. For that reason, the R4600 is a re-implementation of the 5-stage Classic RISC pipeline with large (for the time) caches. For a while, this small and low cost device was one of the highest performance microprocessors on the market. While the initial target market of a MIPS laptop computer never materialized, this device found success in several markets. It was the first RISC processor used within a Cisco Systems network router. It was used in several Atari/Midway arcade games such as the well-known original Mortal Kombat game. The R4600 was licensed by IDT and Toshiba who manufactured and sold the devices.
The R4700 was targeted at SGI, who wanted a little more floating point performance. The R4700 improved on the repeat rate of floating point multiply instructions. This device was used inside the SGI Indy low-end workstation. The R4700 was licensed by IDT and Toshiba who manufactured and sold the devices.
The R4650 was commissioned by NKK, who desired a cheaper implementation for a video console game machine. The R4650 achieved a smaller die area by cutting the caches in half, only implementing single precision floating-point. This device was the first QED device that implemented the multiply–accumulate instructions, which enabled software functions such as softmodem. This device was used in the original Microsoft WebTV device. The R4650 was licensed by IDT and NKK who manufactured and sold the devices. The R4640 was the same chip but with the system bus restricted to 32-bits instead of 64-bits.
The R5000 was commissioned by SGI. This device doubled the instruction and data caches to 32 KB. It implemented a high-performance, fully pipelined floating point unit with multiply–accumulate capability and a SRT divider. The device had a limited implementation of superscalar instruction issue in which one integer instruction and one floating-point instruction could be issued in one cycle. This device was used in the SGI O2 and SGI Indy low-end workstations. The design was owned by SGI, which licensed the design to IDT and NEC and eventually to Toshiba.
The PowerPC 603q was commissioned by Motorola and the target market was Apple Computer's low-cost accounts including a home computer for students and a home video console game named Pippen. The 603q was basically the R4600 pipeline re-targeted for the PowerPC instruction set. Since the PowerPC 603 was then the most power-efficient chip from the AIM alliance, the name of this device was chosen to reflect its low-cost and low-power characteristics. Once those Apple projects were cancelled, Motorola stopped the development of the 603q even though QED had received first silicon samples and they were functional.
The RM52XX series was the first product line sold directly by QED. The first of the series was a cost-reduced version of the R5000 with smaller caches and a different pin-out. The earlier RM52X0 devices had only 16 KB caches while the later RM52X1 devices had 32 KB caches. The RM523X devices had 32-bit system buses while RM526X had 64-bit system buses. This product line was very successful in the laser printer market, winning many accounts at printer companies such as Hewlett-Packard, Lexmark, Ricoh, Samsung.
The RM70XX series was the second product line sold directly by QED. It implemented a large 256 KB on-chip level 2 cache. The RM7000 was one of the first microprocessors to do so, especially within the embedded microprocessor market segment. It also implemented symmetric superscalar instruction issue with two integer execution units. The RM7061 device was a pin-compatible upgrade for the RM526X series. This product line was a very successful follow-on to the RM52XX products.
The RM9x00 family was the first SOC implemented by QED. The Apollo microprocessor core that was part of the RM9x00 had its pipeline lengthened to 7 stages to enable higher operating frequencies. Dynamic branch prediction was added to ameliorate the longer branch latencies. Within the RM9x00, two Apollo cores were used to implement a dual-core device. These processor cores successfully achieved their operating frequency target of 1 GHz. The SOC system interconnect was an in-house design with centralized storage for the transactions flowing through the SOC. Peripherals included a DDR memory controller, a SysAD bus controller, a boot bus controller, a DMA controller and a Hypertransport controller. A second generation device added a Gigabit Ethernet controller, a PCI controller and cache coherency. This product family was not successful due to being late to the market. The company was financially conservative during the time leading up to and after the company's initial public offering and would not fully staff the SOC project. One of the reasons for selling the company to PMC-Sierra was to fund these SOC projects. By that time, competitors like SiByte had already entered the market with equivalent devices.
MIPS is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.
In computer engineering, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler given simpler instructions.
The StrongARM is a family of computer microprocessors developed by Digital Equipment Corporation and manufactured in the late 1990s which implemented the ARM v4 instruction set architecture. It was later acquired by Intel in 1997 from DEC's own Digital Semiconductor division as part of a settlement of a lawsuit between the two companies over plagiarism. Intel then continued to manufacture it before replacing it with the StrongARM-derived ARM-based follow-up architecture called XScale in the early 2000s.
The 88000 is a RISC instruction set architecture developed by Motorola during the 1980s. The MC88100 arrived on the market in 1988, some two years after the competing SPARC and MIPS. Due to the late start and extensive delays releasing the second-generation MC88110, the m88k achieved very limited success outside of the MVME platform and embedded controller environments. When Motorola joined the AIM alliance in 1991 to develop the PowerPC, further development of the 88000 ended.
Intel's i960 was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller. It became a best-selling CPU in that segment, along with the competing AMD 29000. In spite of its success, Intel stopped marketing the i960 in the late 1990s, as a result of a settlement with DEC whereby Intel received the rights to produce the StrongARM CPU. The processor continues to be used for a few military applications.
The Indy, code-named "Guinness", is a low-end multimedia workstation introduced on July 12, 1993. Silicon Graphics Incorporated (SGI) developed, manufactured, and marketed Indy as the lowest end of its product line, for computer-aided design (CAD), desktop publishing, and multimedia markets. It competed with Intel x86 computers, and with Windows and Macintosh, including using their files and running their applications via software emulation. It is the first computer to come standard with a video camera, called IndyCam. Indy was repackaged as a server model called Challenge S. Indy was discontinued on June 30, 1997 and support ended on December 31, 2011.
The AT&T Hobbit is a microprocessor design that AT&T Corporation developed in the early 1990s. It was based on the company's CRISP design, which in turn grew out of the C Machine design by Bell Labs of the late 1980s. All were optimized for running code compiled from the C programming language.
The MIPS Magnum was a line of computer workstations designed by MIPS Computer Systems, Inc. and based on the MIPS series of RISC microprocessors. The first Magnum was released in March, 1990, and production of various models continued until 1993 when SGI bought MIPS Technologies. SGI cancelled the MIPS Magnum line to promote their own workstations including the entry-level SGI Indy.
Advanced RISC Computing (ARC) is a specification promulgated by a defunct consortium of computer manufacturers, setting forth a standard MIPS RISC-based computer hardware and firmware environment. The firmware on Alpha machines that are compatible with ARC is known as AlphaBIOS, non-ARC firmware on Alpha is known as SRM.
The Jazz computer architecture is a motherboard and chipset design originally developed by Microsoft for use in developing Windows NT. The design was eventually used as the basis for most MIPS-based Windows NT systems.
The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers are Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture is known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaces the R8000 in the high-end and the R4400 elsewhere. MTI was a fabless semiconductor company; the R10000 was fabricated by NEC and Toshiba. Previous fabricators of MIPS microprocessors such as Integrated Device Technology (IDT) and three others did not fabricate the R10000 as it was more expensive to do so than the R4000 and R4400.
The R3000 is a 32-bit RISC microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor. It operated at 20, 25 and 33.33 MHz.
The R4000 is a microprocessor developed by MIPS Computer Systems that implements the MIPS III instruction set architecture (ISA). Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation. In the early 1990s, when RISC microprocessors were expected to replace CISC microprocessors such as the Intel i486, the R4000 was selected to be the microprocessor of the Advanced Computing Environment (ACE), an industry standard that intended to define a common RISC platform. ACE ultimately failed for a number of reasons, but the R4000 found success in the workstation and server markets.
The R5000 is a 64-bit, bi-endian, superscalar, in-order execution 2-issue design microprocessor, that implements the MIPS IV instruction set architecture (ISA) developed by Quantum Effect Design (QED) in 1996. The project was funded by MIPS Technologies, Inc (MTI), also the licensor. MTI then licensed the design to Integrated Device Technology (IDT), NEC, NKK, and Toshiba. The R5000 succeeded the QED R4600 and R4700 as their flagship high-end embedded microprocessor. IDT marketed its version of the R5000 as the 79RV5000, NEC as VR5000, NKK as the NR5000, and Toshiba as the TX5000. The R5000 was sold to PMC-Sierra when the company acquired QED. Derivatives of the R5000 are still in production today for embedded systems.
The R8000 is a microprocessor chipset developed by MIPS Technologies, Inc. (MTI), Toshiba, and Weitek. It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the TFP, for Tremendous Floating-Point, its name during development.
The PowerPC 600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance. Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for personal computers. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620.
The R2000 is a 32-bit microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in January 1986, it was the first commercial implementation of the MIPS architecture and the first commercial RISC processor available to all companies. The R2000 competed with Digital Equipment Corporation (DEC) VAX minicomputers and with Motorola 68000 and Intel Corporation 80386 microprocessors. R2000 users included Ardent Computer, DEC, Silicon Graphics, Northern Telecom and MIPS's own Unix workstations.
The R4200 is a microprocessor designed by MIPS Technologies, Inc. (MTI) that implemented the MIPS III instruction set architecture (ISA). It was also known as the VRX during development. The microprocessor was licensed to NEC, and the company fabricated and marketed it as the VR4200. The first VR4200, an 80 MHz part, was introduced in 1993. A faster 100 MHz part became available in 1994.
The R4600, code-named "Orion", is a microprocessor developed by Quantum Effect Design (QED) that implemented the MIPS III instruction set architecture (ISA). As QED was a design firm that did not fabricate or sell their designs, the R4600 was first licensed to Integrated Device Technology (IDT), and later to Toshiba and then NKK. These companies fabricated the microprocessor and marketed it. The R4600 was designed as a low-end workstation or high-end embedded microprocessor. Users included Silicon Graphics, Inc. (SGI) for their Indy workstation and DeskStation Technology for their Windows NT workstations. The R4600 was instrumental in making the Indy successful by providing good integer performance at a competitive price. In embedded systems, prominent users included Cisco Systems in their network routers and Canon in their printers.
Since 1985, many processors implementing some version of the MIPS architecture have been designed and used widely.
Quantum Effect Devices, a company that develops embedded microprocessors for routers, network computers, set-top boxes and other equipment, closed at $56.50, compared with an offering price of $16.
The chip maker PMC-Sierra Inc. said yesterday that it would buy Quantum Effect Devices Inc., a maker of microprocessors used in consumer electronics, in a stock swap worth $2.3 billion based on Tuesday's closing prices ... The deal will give PMC a strong presence in the design of high-speed networks and adds a missing component to its product line