CRUVI FPGA Card

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The CRUVI FPGA Card is a daughter card standard specifically tailored to the needs of FPGAs.

Contents

CRUVI FPGA Card Logo CRUVI Logo.png
CRUVI FPGA Card Logo

Background

The expansion bus interface is designed to create an open ecosystem of function modules for high-performance peripheral connectivity. Its main focus is on supporting FPGA and FPGA SoC devices from all major manufacturers like Altera, Lattice, Microchip and Xilinx.

The word "CRUVI" is a combination of the Estonian word "KRUVI" for screw and the letter "C", which refers to the half of the hexagonal screw head. In this case, the "K" was replaced with "C" to emphasize the reference to the screw head.

Overview

It can be used to build high performance prototypes, for system integration and testing to build complex systems from smaller building blocks to iterate quickly and reduce cost. Create custom test systems for production functional testing.

The carrier module supplies the power supply, the input/output voltage and controls the functions of the peripheral modules.

The CRUVI open standard coexists between low speed, low pin-count like Pmod Interface devices and high-performance, high pin-count (HPC), 400 I/O FPGA Mezzanine Card (FMC) peripherals.

Three board-to-board connectors are specified: CRUVI-LS (Low Speed), CRUVI-HS (High Speed) and CRUVI-GT (Gigabit Transceiver) PCIe Gen 5.0 capable.

Bridging adapter exists to convert signals from Pmod to CRUVI-LS (CR00025), from FMC to CRUVI-HS (CR00101, CR00111) and FMC to CRUVI-GT (CR00112).

History of CRUVI specification

International contributors to define the open source CRUVI specification are Trenz Electronic GmbH, Arrow Electronics, Samtec, Flinders University, Synaptic Laboratories Ltd, Symbiotic EDA and MicroFPGA UG.

YearVersionNotesRefs
20211.0.7 -alphafirst release
20242.0.1 -alphaCRUVI-GT (Gigabit Transceiver) [1]

CRUVI connector specification

specification of connectors
LS Low SpeedHS High SpeedGT Gigabit Transceiver
Carrier side connectorCLT-106-02-F-D-A-KSS4-30-3.50-L-D-KADF6-20-03.5-L-4-2
3D STEP Model CLT-106-02-F-D-A-K 3D Model STEP.jpg SS4-30-3.50-L-D-K 3D Model STEP.jpg ADF6-20-03.5-L-4-2 3D Model STEP.jpg
Peripheral side connectorTMMH-106-04-F-DV-A-MST4-30-1.50-L-D-PADM6-20-01.5-L-4-2
3D STEP Model TMMH-106-04-F-DV-A-M 3D Model STEP.jpg ST4-30-1.50-L-D-P 3D Model STEP.jpg ADM6-20-01.5-L-4-2 3D Model STEP.jpg
Pin no12 (6 per row)60 (30 per row)80 (20 per row)
pitch [mm] / [inch]2 / 0.7870.4 / 0.0160.635 / 0.025
stacked height [mm] / [inch]4.78 to 5.29 /0.188 to 0.2085 / 0.197
speed rating [GHz] / [Gbps]5.5 / 1113.5 / 27 (single ended)

15.5 / 31 (differential)

32
Single ended I/O pins (VCCIO)837 (28 adj.) + (9 fixed 3.3V)8 + I2C
max. differential I/Onomax. 12 LVDSmax. 4 lanes + REFCLK
Power Supplyadjustable, 3.3V, 5V
Current rating per pin [A]4.1 (2-pin powered)1.6 (2-pin powered)1.34 (4-pin powered)
max. Temperatur range [°C]-55 to 125

Structure and description of the carrier modules

Single, double or triple width modules are allowed and they have more mounting holes.

A triple size of space on carrier board is 67.72 x 57.5 mm2 (2.66535 x 2.26378 inch²). There are 3 slots. The mounting holes (1 to 6) for M2 screws are 2.2 mm (0.0866 inch) diameter and need SMD spacer for mechanically fixing. The CR99201 PCB template has LS and HS connectors named: AX, BY and CZ. The CR99500 [2] PCB template has LS, HS and GT connectors.

Structure and description of the peripheral modules

There are different single peripheral module possible, flexible and scalable by size LS, HS and GT connectors. Mounting holes are for M2 screws 2.2 mm (0.0866 inch) diameter.

Templates for the peripheral modules

It is recommended to have EEPROM with I2C for identification of peripheral module with a specific address number.

CRUVI peripheral boards
L x H [mm2] / [inch²]speedPCB template [2] Note
14 x 14 / 0.55 x 0.55LSCR99001 CR99001 CR99002 14 x 14 LS.jpg

identification EEPROM is included; This template is useful for I2C, I3C, SPI sensor, I2S PDM MEMS microphones, programmable oscillator, ADC, DAC or SPI (QSPI) Flash memory device in BGA24 or SO-8 package.

14 x 14 / 0.55 x 0.55LSCR99002same as CR99001 with added u.Fl connectors for I/O
22 x 32 / 0.87 x 1.2598LSCR99003 CR99003 22 x 32 LS.jpg

maximum size one-wide half-length, identification EEPROM is included

18 x 32 / 0.71 x 1.26LSCR99004 CR99004 18 x 32 LS.jpg

This template is useful to convert into Pmod compatible connector (CR00005).

22 x 30 / 0.87 x 1.18LSCR99005 CR99005 22 x 30 LS.jpg

is half-length LS module with two SMA connectors

18 x 20 / 0.71 x 0.79HSCR99101 CR99101 18 x 20 HS.jpg

minimal size HS Module; good for HyperRAM or HyperFlash (CR00041), eMMC (CR00049) or loopback adapter for CRUVI-HS (CR00091)

22 x 57.5 / 0.87 x 2.26HSCR99102 CR99102 22 x 57.5 HS.jpg

maximum sized single-width HS module; good for signal test adapter to probed with scope or logic analyzer (CR00026), for high speed interfaces like USB-C, HDMI (CR00240), MIPI CSI/DSI, SDIO, xGMII Ethernet (CR0020x) and LVDS ADC (1 to 4 data lane)

22 x 57.5 / 0.87 x 2.26GTCR99400 CR99400 22 x 57.5 GT.jpg

This template is suitable for HDMI output (CR00240), JESD204B ADC (CR00401), loopback adapter for CRUVI-GT (CR00092)

Pinout and signal description

CRUVI-LS pinout and signal description

CRUVI-LS pinout and signal description
PinPrimarySignalPinPrimarySignal
1SDA I2C(SDA), SMBUS(SDA)7D1 UART(RXD1), SD(D1), SPI(MISO), QSPI(D1), JTAG(TDI)
2SCLI2C(SCL), SMBUS(SCL)8CLKUART(RTS), SD(CLK), SPI(CLK), QSPI(CLK), JTAG(TCK)
3D3UART(RST), SD(TXD0), QSPI(D3), JTAG(nRST)9D0UART(TXD1), SD(D0), SPI(MOSI), QSPI(D0) JTAG(TDO)
4SELUART(CTS), SD(CMD), SPI(SEL), QSPI(SEL), JTAG(TMS)10VCCPower 3.3V
5D2SMBUS(INT), UART(RXD0), SD(D2), QSPI(D2), JTAG(RFU)11RFUtbd
6GNDGround12VBUSPower 5V

CRUVI-HS pinout and signal description

CRUVI-HS signal description
PinPrimary FunctionNotePinPrimary FunctionNotePinPrimary FunctionNotePinPrimary FunctionNote
1RFU116A0_NLVDS31GNDGround46A5_NLVDS
2HSIO17B0_NLVDS32A3_P47B5_NLVDS
3ALERT/IRQ18GNDGround33B3_PLVDS48GNDGround
4VCC3,3V19GNDGround34A3_N49GNDGround
5SDA20A1_PLVDS35B3_NLVDS50RFU2_P
6HSO21B1_PLVDS36VADJ1.2 to 3.3V51DI/TDIJTAG, SPI(MISO)
7SCL22A1_NLVDS37GNDGround52RFU2_N
8HSRST23B1_NLVDS38A4_PLVDS53DO/TDOJTAG, SPI(MOSI)
9VCC3.3V24GNDGround39B4_PLVDS54GNDGround
10HSI25GNDGround40A4_NLVDS55SEL/TMSJTAG, SPI(SEL)
11REFCLK26A2_P41B4_NLVDS56RFU_P
12GNDGround27B2_PLVDS42GNDGround57MODEJTAG EN
13GNDGround28A2_N43GNDGround58RFU_N
14A0_PLVDS29B2_NLVDS44A5_PLVDS59SCK/TCKJTAG, SPI(CLK)
15B0_PLVDS30GNDGround45B5_PLVDS60VBUS5V

CRUVI-GT pinout and signal description

CRUVI-GT signal description
PinPrimary FunctionNotePinPrimary FunctionNotePinPrimary FunctionNotePinPrimary FunctionNote
A1GNDGroundB1TCKJTAGC1TDIJTAGD1GNDGround
A2TX3_NB2TMSJTAGC2TDOJTAGD2RX3_N
A3TX3_PB3C3D3RX3_P
A4GNDGroundB4C4D4GNDGround
A5TX2_NB5C5D5RX2_N
A6TX2_PB6C6D1_ND6RX2_P
A7GNDGroundB7C7D1_PD7GNDGround
A8B8C8D8CLK0_NCLK
A9B9C9D9CLK0_PCLK
A10B10VADJ1.2 to 3.3VC10VCC_5V5VD10GNDGround
A11B11VCC_3.3V3.3VC11VCC_12V12VD11GNDGround
A12B12C12D12GBTCLK0_NCLK
A13B13C13D13GBTCLK0_PCLK
A14GNDGroundB14C14D0_ND14GNDGround
A15TX1_NB15C15D0_PD15RX1_N
A16TX1_PB16S4_LSAUX IOC16S7_LSAUX IOD16RX1_P
A17GNDGroundB17S5_LSAUX IOC17S6_LSAUX IOD17GNDGround
A18TX0_NB18S0_LSAUX IOC18S3_LSAUX IOD18RX0_N
A19TX0_PB19S1_LSAUX IOC19S2_LSAUX IOD19RX0_P
A20GNDGroundB20SDA_LSSMBusC20SCL_LSSMBUsD20GNDGround

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References

  1. "CRUVI specification v2.0.1 (2024)" (PDF). GitHub . Retrieved 2024-05-17.
  2. 1 2 "PCB template CRUVI boards". GitHub . Retrieved 2024-05-17.