Engineering change order

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An engineering change order (ECO), also called an engineering change notice (ECN), engineering change (EC), or engineering release notice(ERN), is an artifact used to implement changes to components or end products. The ECO is utilized to control and coordinate changes to product designs that evolve over time.

Contents

The need for an engineering change may be triggered by a number of events and varies by industry. Typical engineering change categories are:

Usage and contents

An ECO is defined as "[A] document approved by the design activity that describes and authorizes the implementation of an engineering change to the product and its approved configuration documentation". [1]

In product development the need for change is caused by:

An ECO must contain at least this information: [2]

Chip design

In chip design, ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC logic synthesis, technology mapping, place, route, layout extraction, and timing verification. EDA tools are often built with incremental modes of operation to facilitate this type of ECO.

After masks have been made, ECOs may be done to save money. If a change can be implemented by modifying only a few of the layers (typically metal) then the cost is much less than it would be if the design was re-built from scratch. This is because starting the process from the beginning will almost always require new photomasks for all layers, and each of the 20 or so masks in a modern semiconductor fabrication process is quite expensive. A change implemented by modifying only a few layers is typically called a metal-mask ECO or a post-mask ECO. Designers often sprinkle a design with unused logic gates, and EDA tools have specialized commands, to make this process easier.

One of the most common ECOs in ASIC design is the gate-level netlist ECO. In this flow, engineers manually (and often tediously) hand-edit the gate-level netlist, instead of re-running logic synthesis. The netlist files have to be searched for the logic affected by the change, the files need to be edited to implement the changes up and down the hierarchy, and the changes need to be tracked and verified to make sure exactly what needs to change gets changed and nothing more. This is a very time and resource-intensive process that is easily subject to errors. Therefore formal equivalence checking is normally used after ECOs to ensure the revised implementation matches the revised specification.

With time-to-market pressures and rising mask costs in the semiconductor industry, several electronic design automation (EDA) companies are beginning to bring more automation into the ECO implementation process. Most popular place and route products have some level of built-in ECO routing to help with implementing physical-level ECOs. Cadence Design Systems has recently announced a product called conformal ECO designer, that automates the creation of Functional ECOs, usually the most tedious process in implementing an ECO. It uses formal equivalence checking and logic synthesis techniques to produce a gate-level ECO netlist based on the changed RTL. Synopsys in the past had a product called ECO compiler that is now defunct. Synopsys now has primetime-ECO for dealing with ECOs. [4] Tweaker-F1 & Tweaker-T1 have also come into the limelight in the recent DAC-2012 for their ECO algorithms. [5]

Telecommunications industry

The telecommunications industry has a formal process that takes elements of the ECO and other considerations and combines them into the "product change notice" (PCN). After telecommunications products have been generally available and/or in service for a period of time, it often becomes necessary for suppliers to introduce changes to those products. As a result of implementing these changes – regardless of who performs the actual work – the telecommunications carriers are significantly impacted with respect to labor and resources, etc. Thus, it is imperative that changes to these products are accurately reported and tracked through completion, according to the needs and requirements of the carriers.

The term "product change" includes changes to hardware, software, and firmware that occur over the entire life of a product. Product changes include those considered reportable and non-reportable. These changes may be applied by a supplier, a customer, or a contractor retained by the customer, depending on negotiated agreements. Fundamentally, the customer's goal is to ensure there is a process by which there is accurate and efficient tracking and reporting of changes to products.

Changes are considered reportable when they affect the performance or life span of a product. Such changes include any that affect the form, fit, function, or the product technical specification (i.e., documentation) of the product. The desire for supplier or customer traceability may result in a reportable change.

The entire PCN process is documented in GR-209, Issue 6, Generic Requirements for Product Change Notices (PCNs).

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Physical design (electronics)

In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called integrated circuit layout. This step is usually split into several sub-steps, which include both design and verification and validation of the layout.

EVE/ZeBu Provider of hardware-assisted verification tools

EVE/ZeBu is a provider of hardware-assisted verification tools for functional verification of Application-specific integrated circuits (ASICs) and system on chip (SOC) designs and for validation of embedded software ahead of implementation in silicon. EVE's hardware acceleration and hardware emulation products work in conjunction with Verilog, SystemVerilog, and VHDL-based simulators from Synopsys, Cadence Design Systems and Mentor Graphics. EVE's flagship product is ZeBu.

NanGate, Inc was a privately held US/Silicon Valley-based multinational corporation dealing in Electronic Design Automation (EDA) for electrical engineering and electronics until its acquisition by Silvaco, Inc. in 2018. NanGate was founded in October 2004 by a group of semiconductor professionals with a background from Intel Corporation and Vitesse Semiconductor Corp. The company has received capital investments from a group of Danish business angels and venture capital companies. The company is today owned and controlled by its management following a management buy-out in 2012. NanGate markets a range of software products and design services for the design and optimization of standard cell libraries and application-specific integrated circuits. The market focus is standard cell library design and optimization for 14-28 nanometer CMOS processes.

References

  1. ↑ Buckley, Fletcher J. (1996) Implementing Configuration Management: Hardware, Software and Firmware. 2nd Edition. IEEE.
  2. ↑ Ullman, David G. (2009) The Mechanical Design Process, Mc Graw Hill, 4th edition .
  3. ↑ A free Word template with fields for this information is available associated with Ullman.
  4. ↑ "Signoff-Driven ECO Guidance for Faster Timing Closure". Archived from the original on 2013-02-03. Retrieved 2012-06-02.
  5. ↑ "Synopsys Mentor Cadence TSMC GlobalFoundries SNPS MENT CDNS". Archived from the original on 2013-02-01.
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