Giovanni De Micheli

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Giovanni De Micheli
Occupation(s)Electrical engineer and educator
Academic background
Alma mater
Thesis Computer-Aided Synthesis of PLA-Based Systems
Doctoral advisor Alberto Sangiovanni-Vincentelli

Giovanni De Micheli is a research scientist in electronics and computer science. He is credited for the invention of the Network on a Chip design automation paradigm and for the creation of algorithms and design tools for Electronic Design Automation (EDA). He is Professor and Director of the Integrated Systems laboratory at École Polytechnique Fédérale de Lausanne (EPFL), Switzerland. Previously, he was Professor of Electrical Engineering at Stanford University. He was Director of the Electrical Engineering Institute at EPFL from 2008 to 2019 and program leader of the Swiss Federal Nano-Tera.ch program. He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California, Berkeley, 1980 and 1983) under Alberto Sangiovanni-Vincentelli. [2] [3] [4]

Contents

De Micheli is a Fellow of ACM, AAAS [5] and IEEE; a Member of the Academia Europaea [2] and an International Honorary Member of the American Academy of Arts and Sciences. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of Synthesis and Optimization of Digital Circuits (McGraw-Hill, 1994) [6] and co-author and/or co-editor of ten other books [7] and of over 950 publications. His citation h-index is above 100 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B) and STMicroelectronics. He has chaired several conferences, including DATE (2010), [8] pHealth (2006), VLSI SOC (2006), [9] DAC (2000) and ICCD (1989). [10] [2]

Honors and awards

Prof. De Micheli is the recipient of the 2023 Phil Kaufman award for distinguished contributions to EDA; the 2020 IEEE/TC Achievement Award in Cyberphysical Systems, for sustained contributions to smart sensors, wearable and implanted electronics, and cyber-medical systems; the 2020 IEEE/CEDA Richard Newton Technical Impact Award for "Networks on Chips: a New SoC Paradigm"; the 2019 ACM/SIGDA Pioneering Achievement Award,for pioneering and fundamental contributions to synthesis and optimization of integrated circuits and networks on chips; [2] [11] the 2016 EDAA Lifetime Achievement Award; the 2016 IEEE/CS Harry H. Goode Memorial Award for seminal contributions to design and design tools of Networks on Chips; the 2012 IEEE/CAS Mac Van Valkenburg Award for contributions to theory, practice and experimentation in design methods and tools and the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems.

His PhD students include Luca Benini, [12] Rajesh K. Gupta, Jerry Yang, Vincent Mooney, Sungroh Yoon, E.Y. Chung, S. Murali, Irene Taurino, Francesca Puppo, Luca Amaru and Tajana Rosing.

Selected publications

Related Research Articles

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to integrated circuits (ICs).

The Phil Kaufman Award for Distinguished Contributions to EDA honors individuals for their impact on electronic design by their contributions to electronic design automation (EDA). It was established in 1994 by the EDA Consortium. The IEEE Council on Electronic Design Automation (CEDA) became a co-sponsor of the award. The first Phil Kaufman Award was presented in 1994.

Placement is an essential step in electronic design automation — the portion of the physical design flow that assigns exact locations for various circuit components within the chip's core area. An inferior placement assignment will not only affect the chip's performance but might also make it non-manufacturable by producing excessive wire-length, which is beyond available routing resources. Consequently, a placer must perform the assignment while optimizing a number of objectives to ensure that a circuit meets its performance demands. Together, the placement and routing steps of IC design are known as place and route.

The primary focus of this article is asynchronous control in digital electronic systems. In a synchronous system, operations are coordinated by one, or more, centralized clock signals. An asynchronous system, in contrast, has no global clock. Asynchronous systems do not depend on strict arrival times of signals or messages for reliable operation. Coordination is achieved using event-driven architecture triggered by network packet arrival, changes (transitions) of signals, handshake protocols, and other methods.

<span class="mw-page-title-main">Network on a chip</span> Electronic communication subsystem on an integrated circuit

A network on a chip or network-on-chip is a network-based communications subsystem on an integrated circuit ("microchip"), most typically between modules in a system on a chip (SoC). The modules on the IC are typically semiconductor IP cores schematizing various functions of the computer system, and are designed to be modular in the sense of network science. The network on chip is a router-based packet switching network between SoC modules.

Jingsheng Jason Cong is a Chinese-born American computer scientist, educator, and serial entrepreneur. He received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. He has been on the faculty in the Computer Science Department at the University of California, Los Angeles (UCLA) since 1990. Currently, he is a Distinguished Chancellor’s Professor and the director of Center for Domain-Specific Computing (CDSC).

Logic optimization is a process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. This process is a part of a logic synthesis applied in digital electronics and integrated circuit design.

Aart J. de Geus is a co-founder and executive chair of Synopsys Inc., where he was CEO until January 2024.

Sung-Mo "Steve" Kang is an American electrical engineering scientist, professor, writer, inventor, entrepreneur and 15th president of KAIST. Kang was appointed as the second chancellor of the University of California, Merced in 2007. He was the first department head of foreign origin at the electrical and computer engineering department at the University of Illinois at Urbana-Champaign and Dean of the Baskin School of Engineering at UC Santa Cruz. Kang teaches and has written extensively in the field of computer-aided design for electronic circuits and systems; he is recognized and respected worldwide for his outstanding research contributions. Kang has led the development of the world’s first 32-bit microprocessor chips as a technical supervisor at AT&T Bell Laboratories and designed satellite-based private communication networks as a member of technical staff. Kang holds 15 U.S. patents and has won numerous awards for his ground breaking achievements in the field of electrical engineering.

Nikil Dutt is a Chancellor's Professor of Computer Science at University of California, Irvine, United States. Professor Dutt's research interests are in embedded systems, electronic design automation, computer architecture, optimizing compilers, system specification techniques, distributed systems, and formal methods.

MULTICUBE is a Seventh Framework Programme (FP7) project aimed to define innovative methods for the design optimization of computer architectures for the embedded system domain.

Prabhu Goel is an Indian American researcher, entrepreneur and businessman, known for having developed the PODEM Automatic test pattern generation and Verilog hardware description language.

<span class="mw-page-title-main">Massoud Pedram</span> Iranian American computer engineer

Massoud Pedram is an Iranian American computer engineer noted for his research in green computing, energy storage systems, low-power electronics and design, electronic design automation and quantum computing. In the early 1990s, Pedram pioneered an approach to designing VLSI circuits that considered physical effects during logic synthesis. He named this approach layout-driven logic synthesis, which was subsequently called physical synthesis and incorporated into the standard EDA design flows. Pedram's early work on this subject became a significant prior art reference in a litigation between Synopsys Inc. and Magma Design Automation.

<span class="mw-page-title-main">Saraju Mohanty</span> Indian-American computer scientist

Saraju Mohanty is an Indian-American professor of the Department of Computer Science and Engineering, and the director of the Smart Electronic Systems Laboratory, at the University of North Texas in Denton, Texas. Mohanty received a Glorious India Award – Rich and Famous NRIs of America in 2017 for his contributions to the discipline. Mohanty is a researcher in the areas of "smart electronics for smart cities/villages", "smart healthcare", "application-Specific things for efficient edge computing", and "methodologies for digital and mixed-signal hardware". He has made significant research contributions to security by design (SbD) for electronic systems, hardware-assisted security (HAS) and protection, high-level synthesis of digital signal processing (DSP) hardware, and mixed-signal integrated circuit computer-aided design and electronic design automation. Mohanty has been the editor-in-chief (EiC) of the IEEE Consumer Electronics Magazine during 2016-2021. He has held the Chair of the IEEE Computer Society's Technical Committee on Very Large Scale Integration during 2014-2018. He holds 4 US patents in the areas of his research, and has published 500 research articles and 5 books. He is ranked among top 2% faculty around the world in Computer Science and Engineering discipline as per the standardized citation metric adopted by the Public Library of Science Biology journal.

Bus encoding refers to converting/encoding a piece of data to another form before launching on the bus. While bus encoding can be used to serve various purposes like reducing the number of pins, compressing the data to be transmitted, reducing cross-talk between bit lines, etc., it is one of the popular techniques used in system design to reduce dynamic power consumed by the system bus. Bus encoding aims to reduce the Hamming distance between 2 consecutive values on the bus. Since the activity is directly proportional to the Hamming distance, bus encoding proves to be effective in reducing the overall activity factor thereby reducing the dynamic power consumption in the system.

<span class="mw-page-title-main">Eby Friedman</span>

Eby G. Friedman is an electrical engineer, and Distinguished Professor of Electrical and Computer Engineering at the University of Rochester. Friedman is also a visiting professor at the Technion - Israel Institute of Technology. He is a Senior Fulbright Fellow and a Fellow of the IEEE.

<span class="mw-page-title-main">David Atienza</span> Spanish physicist and materials scientist

David Atienza Alonso is a Spanish/Swiss scientist in the disciplines of computer and electrical engineering. His research focuses on hardware‐software co‐design and management for energy‐efficient and thermal-aware computing systems, always starting from a system‐level perspective to the actual electronic design. He is a full professor of electrical and computer engineering at the Swiss Federal Institute of Technology in Lausanne (EPFL) and the head of the Embedded Systems Laboratory (ESL). He is an IEEE Fellow (2016), and an ACM Fellow (2022).

Krishnendu Chakrabarty is an Indian-American electrical and computer engineer. He is the Fulton Professor of Microelectronics at Arizona State University Ira A. Fulton Schools of Engineering. Before joining Arizona State, he was the John Cocke Distinguished Professor and was the Chair of the Department of Electrical and Computer Engineering at Duke University Pratt School of Engineering.

Luca Benini is a computer scientist who is a Professor of Electronics at University of Bologna and the Chair of Digital Circuits and Systems at ETH Zurich.

<span class="mw-page-title-main">Igor L. Markov</span> American computer scientist and engineer

Igor Leonidovich Markov is an American professor, computer scientist and engineer. Markov is known for mathematical and algorithmic results in quantum computation, work on limits of computation, research on algorithms for optimizing integrated circuits and on electronic design automation, as well as artificial intelligence. Additionally, Markov is a California non-profit executive responsible for aid to Ukraine worth tens of millions dollars.

References

  1. ↑ "Giovanni De Micheli". Giovanni De Micheli. Retrieved 4 September 2022.
  2. 1 2 3 4 "Giovanni De Micheli | IEEE Computer Society". 11 April 2018. Retrieved 2 May 2022.
  3. ↑ "Computer-Aided Synthesis of PLA-Based Systems". Technical Reports. Retrieved 4 September 2022.
  4. ↑ "Giovanni de Micheli". The Mathematics Genealogy Project. Retrieved 4 September 2022.
  5. ↑ "2021 AAAS Fellows | American Association for the Advancement of Science". [American Association for the Advancement of Science]]. Retrieved 2 May 2022.
  6. ↑ De Micheli, Giovanni, ed. (1994). Synthesis and Optimization of Digital Circuits. McGraw Hill. ISBN   978-0-07-016333-1.
  7. ↑ "Giovanni De Micheli". Google Scholar . Retrieved 21 May 2022.
  8. ↑ "Proceedings of the Conference on Design, Automation and Test in Europe". Design Automation and Test in Europe . Retrieved 21 May 2022.
  9. ↑ Micheli, Giovanni De; Mir, Salvador; Reis, Ricardo (23 August 2010). VLSI-SoC: Research Trends in VLSI and Systems on Chip: Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France. Springer. ISBN   978-0-387-74909-9.
  10. ↑ "21st Asia and South Pacific Design Automation Conference (ASP-DAC 2016)". ASP Design Automation Conference. Retrieved 21 May 2022.
  11. ↑ "Harry H. Goode Memorial Award | IEEE Computer Society". 4 April 2018. Retrieved 2 May 2022.
  12. ↑ Benini, Luca (1997). Automatic synthesis of sequential circuits for low power dissipation (Thesis). OCLC   79215310.[ non-primary source needed ]
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