The Hitachi HD44780 LCD controller is an alphanumeric dot matrix liquid crystal display (LCD) controller developed by Hitachi in the 1980s. The character set of the controller includes ASCII characters, Japanese Kana characters, and some symbols in two 40 character lines. Using an extension driver, the device can display up to 80 characters. [1] Numerous third-party displays are compatible with its 16-pin interface and instruction set, making it a popular and cheap LCD driver. [2]
The Hitachi HD44780 LCD controller is limited to monochrome text displays and is often used in copiers, fax machines, laser printers, industrial test equipment, and networking equipment, such as routers and storage devices.
Compatible LCD screens are manufactured in several standard configurations. Common sizes are one row of eight characters (8×1), and 16×2, 20×2 and 20×4 formats. Larger custom sizes are made with 32, 40 and 80 characters and with 1, 2, 4 or 8 lines. The most commonly manufactured larger configuration is 40×4 characters, which requires two individually addressable HD44780 controllers with expansion chips as a single HD44780 chip can only address up to 80 characters.
Character LCDs may have a backlight, which may be LED, fluorescent, or electroluminescent. The nominal operating voltage for LED backlights is 5V at full brightness, with dimming at lower voltages dependent on the details such as LED color. Non-LED backlights often require higher voltages.
Character LCDs use a 16-contact interface, commonly using pins or card edge connections on 0.1 inch (2.54 mm) centers. Those without backlights may have only 14 pins, omitting the two pins powering the light. This interface was designed to be easily hooked up to the Intel MCS-51 XRAM interface, using only two address pins, which allowed displaying text on LCD using simple MOVX commands, offering a cost effective option for adding text display to devices.[ citation needed ]
The predominant pinout is as follows (exceptions exist):
| Pin# | Name | Direction | Description |
|---|---|---|---|
| 1 | Vss | Power | Power Supply Ground |
| 2 | Vcc | Power | Power Supply (+3.3 or +5 V depending on module) |
| 3 | Vee | Input | Contrast Adjustment (analog input) |
| 4 | RS | Input | Register Select (0 = command, 1 = data) |
| 5 | R/W | Input | Read/Write (0 = write to display module, 1 = read from display module) |
| 6 | E | Input | Clock Enable (falling-edge triggered) |
| 7 | DB0 | I/O | Data Bit 0 (not used in 4-bit operation) |
| 8 | DB1 | I/O | Data Bit 1 (not used in 4-bit operation) |
| 9 | DB2 | I/O | Data Bit 2 (not used in 4-bit operation) |
| 10 | DB3 | I/O | Data Bit 3 (not used in 4-bit operation) |
| 11 | DB4 | I/O | Data Bit 4 |
| 12 | DB5 | I/O | Data Bit 5 |
| 13 | DB6 | I/O | Data Bit 6 |
| 14 | DB7 | I/O | Data Bit 7 |
| 15 | LED+ | Power | Backlight Anode (+) (if applicable) |
| 16 | LED− | Power | Backlight Cathode (−) (if applicable) |
Notes:
In 8-bit mode, all transfers happen in one cycle of the enable pin (E) with all 8 bits on the data bus and the RS and R/W pins stable. In 4-bit mode, data are transferred as pairs of 4-bit "nibbles" on the upper data pins, D7–D4, with two enable pulses and the RS and R/W pins stable. The four most significant bits (7–4) must be written first, followed by the four least significant bits (3–0). The high/low sequence must be completed each time or the controller will not properly receive further commands.
Selecting 4-bit or 8-bit mode requires careful selection of commands. There are two primary considerations. First, with D3–D0 unconnected, these lines will always appear high (binary 1111) to the HD44780 since there are internal pull-up MOSFETs. [3] Second, the LCD may initially be in one of three states:
State 3 may occur, for example, if a prior control was aborted after sending only the first 4 bits of a command while the HD44780 was in 4-bit mode.
The following algorithm ensures that the LCD is in the desired mode:
The same command is sent three times, Function Set with 8-bit interface D7–D4 = binary 0011, the lower four bits are "don't care", using single enable pulses. If the controller is in 4-bit mode, the lower four bits are ignored so they cannot be sent until the interface is in a known size configuration.
Starting in state 1 (8-bit configuration):
Starting in state 2 (4-bit configuration, waiting for first 4-bit transfer):
Starting in state 3 (4-bit configuration, waiting for last 4-bit transfer):
In all three starting cases, the bus interface is now in 8-bit mode, 1 line, 5×8 characters. If a different configuration 8-bit mode is desired, an 8-bit bus Function Set command should be sent to set the full parameters. If 4-bit mode is desired, binary 0010 should be sent on D7–D4 with a single enable pulse. Now the controller will be in 4-bit mode and a full 4-bit bus Function Set command sequence (two enables with command bits 7–4 and 3–0 on subsequent cycles) will complete the configuration of the Function Set register.
The HD44780 instruction set is shown below: [4]
| Instruction | Code | Description | Execution time (max) (when fcp = 270 kHz) | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RS | R/W | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | |||
| Clear display | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Clears display and returns cursor to the home position (address 0). | 1.52 ms |
| Cursor home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | * | Returns cursor to home position. Also returns display being shifted to the original position. DDRAM content remains unchanged. | 1.52 ms |
| Entry mode set | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | I/D | S | Sets cursor move direction (I/D); specifies to shift the display (S). These operations are performed during data read/write. | 37 μs |
| Display on/off control | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B | Sets on/off of all display (D), cursor on/off (C), and blink of cursor position character (B). | 37 μs |
| Cursor/display shift | 0 | 0 | 0 | 0 | 0 | 1 | S/C | R/L | * | * | Sets cursor-move or display-shift (S/C), shift direction (R/L). DDRAM content remains unchanged. | 37 μs |
| Function set | 0 | 0 | 0 | 0 | 1 | DL | N | F | * | * | Sets interface data length (DL), number of display line (N), and character font (F). | 37 μs |
| Set CGRAM address | 0 | 0 | 0 | 1 | CGRAM address | Sets the CGRAM address. CGRAM data are sent and received after this setting. | 37 μs | |||||
| Set DDRAM address | 0 | 0 | 1 | DDRAM address | Sets the DDRAM address. DDRAM data are sent and received after this setting. | 37 μs | ||||||
| Read busy flag & address counter | 0 | 1 | BF | CGRAM/DDRAM address | Reads busy flag (BF) indicating internal operation being performed and reads CGRAM or DDRAM address counter contents (depending on previous instruction). | 0 μs | ||||||
| Write CGRAM or DDRAM | 1 | 0 | Write Data | Write data to CGRAM or DDRAM. | 37 μs | |||||||
| Read from CG/DDRAM | 1 | 1 | Read Data | Read data from CGRAM or DDRAM. | 37 μs | |||||||
| Instruction bit names — I/D – 0 = decrement cursor position, 1 = increment cursor position; S – 0 = no display shift, 1 = display shift; D – 0 = display-off, 1 = display on; C – 0 = cursor off, 1 = cursor on; B – 0 = cursor blink off, 1 = cursor blink on; S/C – 0 = move cursor, 1 = shift display; R/L – 0 = shift left, 1 = shift right; DL – 0 = 4-bit interface, 1 = 8-bit interface; N – 0 = 1/8 or 1/11 duty (1 line), 1 = 1/16 duty (2 lines); F – 0 = 5×8 dots, 1 = 5×10 dots; BF – 0 = can accept instruction, 1 = internal operation in progress. | ||||||||||||
DDRAM is Display Data RAM and CGRAM is Character Generator RAM. [5] The DDRAM is 80 bytes (40 per row) addressed with a gap between the two rows. The first row is addresses 0 to 39 decimal or 0 to 27 hex. The second row is addresses 64 to 103 decimal or 40 to 67 hex.
The CGRAM is read/write memory used to encode up to 8 characters in the character generator. It consists of 64 fields at addresses 0 to 3F hex. Each field is 5 bits mapping to a row of pixels of each character. Each 8 fields in the CGRAM are used for each character. The lower 3 bits of the character codes from 0–7 and 8–15 select the groups of 8 fields in the CGRAM memory.
Reading and writing to the DDRAM is done by setting the RS input high during bus transfers. The DDRAM must also be selected by using the Set DDRAM address command which selects the DDRAM for access and also sets the starting address for DDRAM access.
Likewise reading and writing to the CGRAM is done by setting the RS input high during bus transfers. The CGRAM must also be selected by the Set CGRAM address command which selects the CGRAM for access and also sets the starting address for CGRAM access.
The execution times listed in this table are based on an oscillator frequency of 270 kHz. The data sheet indicates that for a resistor of 91 kΩ at VCC=5 V the oscillator can vary between 190 kHz and 350 kHz resulting in wait times of 52.6 µs and 28.6 µs instead of 37 µs. If a display with the recommended 91 kΩ resistor is powered from 3.3 volts the oscillator will run much slower. If the busy bit is not used and instructions are timed by the external circuitry, this should be taken into account.
The original HD44780 character generator ROM contains 208 characters in a 5×8 dot matrix, and 32 characters in a 5×10 dot matrix. More recent compatible chips are available with higher resolution, matched to displays with more pixels.[ citation needed ]
Two versions of the ROM have been developed: [5]
The 7-bit ASCII subset for the Japanese version is non-standard: it supplies a Yen symbol where the backslash character is normally found, and left and right arrow symbols in place of tilde and the rubout character.
A limited number of custom characters can be programmed into the device in the form of a bitmap using special commands. These characters have to be written to the device each time it is switched on, as they are stored in volatile memory.
A liquid-crystal display (LCD) is a flat-panel display or other electronically modulated optical device that uses the light-modulating properties of liquid crystals combined with polarizers. Liquid crystals do not emit light directly but instead use a backlight or reflector to produce images in color or monochrome.
Synchronous dynamic random-access memory is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.
AVR is a family of microcontrollers developed since 1996 by Atmel, acquired by Microchip Technology in 2016. These are modified Harvard architecture 8-bit RISC single-chip microcontrollers. AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time.
In computing, a parallel port is a type of interface found on early computers for connecting peripherals. The name refers to the way the data is sent; parallel ports send multiple bits of data at once, as opposed to serial communication, in which bits are sent one at a time. To do this, parallel ports require multiple data lines in their cables and port connectors and tend to be larger than contemporary serial ports, which only require one data line.
The Intel 4040 microprocessor was the successor to the Intel 4004, introduced in 1974. The 4040 employed a 10 μm silicon gate enhancement-load PMOS technology, was made up of 3,000 transistors and could execute approximately 62,000 instructions per second.
I2C (Inter-Integrated Circuit; pronounced as “eye-squared-see” or “eye-two-see”), alternatively known as I2C or IIC, is a synchronous, multi-controller/multi-target (historically-termed as master/slave), single-ended, serial communication bus invented in 1982 by Philips Semiconductors. It is widely used for attaching lower-speed peripheral ICs to processors and microcontrollers in short-distance, intra-board communication.
The MSP430 is a mixed-signal microcontroller family from Texas Instruments, first introduced on 14 February 1992. Built around a 16-bit CPU, the MSP430 was designed for low power consumption embedded applications and low cost.
Serial Peripheral Interface (SPI) is a de facto standard for synchronous serial communication, used primarily in embedded systems for short-distance wired communication between integrated circuits.
The Display Data Channel, or DDC, is a collection of protocols for digital communication between a computer display and a graphics adapter that enable the display to communicate its supported display modes to the adapter and that enable the computer host to adjust monitor parameters, such as brightness and contrast.
1-Wire is a wired half-duplex serial bus designed by Dallas Semiconductor that provides low-speed (16.3 kbit/s) data communication and supply voltage over a single conductor.
The Motorola 6845, or MC6845, is a display controller that was widely used in 8-bit computers during the 1980s. Originally intended for designs based on the Motorola 6800 CPU and given a related part number, it was more widely used alongside various other processors, and was most commonly found in machines based on the Zilog Z80 and MOS 6502.
A thin-film-transistor liquid-crystal display is a type of liquid-crystal display that uses thin-film-transistor technology to improve image qualities such as addressability and contrast. A TFT LCD is an active matrix LCD, in contrast to passive matrix LCDs or simple, direct-driven LCDs with a few segments.
MIL-STD-1553 is a military standard published by the United States Department of Defense that defines the mechanical, electrical, and functional characteristics of a serial data bus. It was originally designed as an avionic data bus for use with military avionics, but has also become commonly used in spacecraft on-board data handling (OBDH) subsystems, both military and civil, including use on the James Webb space telescope. It features multiple redundant balanced line physical layers, a (differential) network interface, time-division multiplexing, half-duplex command/response protocol, and can handle up to 31 Remote Terminals (devices); 32 is typically designated for broadcast messages. A version of MIL-STD-1553 using optical cabling in place of electrical is known as MIL-STD-1773.
XDR DRAM is a high-performance dynamic random-access memory interface. It is based on and succeeds RDRAM. Competing technologies include DDR2 and GDDR4.
The Epson HX-20 was the first "true" laptop computer. It was invented in July 1980 by Yukio Yokozawa, who worked for Suwa Seikosha, now the Seiko Epson subsidiary of the Japanese Seiko Group, receiving a patent for the invention. It was announced in 1981 as the HC-20 in Japan, and was introduced by Epson in North America as the HX-20 at the 1981 COMDEX computer show in Las Vegas, where it drew significant attention for its portability. It had a mass-market release in July 1982, as the HC-20 in Japan and as the Epson HX-20 in North America. The size of an A4 notebook and weighing 1.6 kg, it was hailed by BusinessWeek magazine as the "fourth revolution in personal computing".
In electronics/computer hardware, a display driver is usually a semiconductor integrated circuit which provides an interface function between a microprocessor, microcontroller, ASIC or general-purpose peripheral interface and a particular type of display device, e.g. LCD, LED, OLED, ePaper, CRT, Vacuum fluorescent or Nixie.
The Display Serial Interface (DSI) is a specification by the Mobile Industry Processor Interface (MIPI) Alliance aimed at reducing the cost of display controllers in a mobile device. It is commonly targeted at LCD and similar display technologies. It defines a serial bus and a communication protocol between the host, the source of the image data, and the device which is the destination. The interface is closed source, which means that the specification of the interface is not open to the public. The maintenance of the interface is the responsibility of the MIPI Alliance. Only legal entities can be members. These members or the persons commissioned and approved by them have access to the specification in order to use it in their possible applications.
The Bus Pirate is a universal bus interface device designed for programming, debugging, and analyzing microcontrollers and other ICs. It was developed as an open-source hardware and software project.
The MSP432 is a mixed-signal microcontroller family from Texas Instruments. It is based on a 32-bit ARM Cortex-M4F CPU, and extends their 16-bit MSP430 line, with a larger address space for code and data, and faster integer and floating point calculation than the MSP430. Like the MSP430, it has a number of built-in peripheral devices, and is designed for low power requirements. In 2021, TI confirmed that the MSP432 has been discontinued and "there will be no new MSP432 products".
The Commodore serial bus, is Commodore's interface for primarily magnetic disk data storage and printers for Commodore 8-bit home computers: the VIC-20, Commodore 64, Commodore 128, Plus/4, Commodore 16, and Commodore 65.