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Compute Express Link (CXL) is an open standard interconnect for high-speed, high capacity central processing unit (CPU)-to-device and CPU-to-memory connections, designed for high performance data center computers. CXL is built on the serial PCI Express (PCIe) physical and electrical interface and includes PCIe-based block input/output protocol (CXL.io) and new cache-coherent protocols for accessing system memory (CXL.cache) and device memory (CXL.mem). The serial communication and pooling capabilities allows CXL memory to overcome performance and socket packaging limitations of common DIMM memory when implementing high storage capacities.
References
- 1 2 Tom Slaight (2007). "Management Component Transport Protocol (MCTP)" (PDF). Intel. Archived from the original (PDF) on November 9, 2013. Retrieved November 9, 2013.
- ↑ Amar Kapadia (June 18, 2012). "MCTP: This protocol is a key tool in server management to maximize ROI". networkworld.com. Retrieved November 9, 2013.
- 1 2 Eliel Louzoun (2013). "MCTP over PCIe Implementation". PCI-SIG. Archived from the original (PDF) on November 9, 2013. Retrieved November 9, 2013.
- ↑ "Management Component Transport Protocol (MCTP) Serial Transport Binding" (PDF). DMTF. July 21, 2010. Retrieved February 26, 2014.
- ↑ "PMCI | DMTF". www.dmtf.org. (list of standards)
- ↑ "Intel Ethernet Controller I210 Datasheet" (PDF). Intel. 2013. pp. 1, 15, 52, 621–776. Retrieved November 9, 2013.
- ↑ "Intel Ethernet Controller X540 Product Brief" (PDF). Intel. 2012. Retrieved February 26, 2014.
- ↑ "Management Component Transport Protocol (MCTP) Host Interface Specification" (PDF). DMTF. July 21, 2010. Retrieved February 26, 2014.
