Multi-project wafer service

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Multi-project chip (MPC), and multi-project wafer (MPW) semiconductor manufacturing arrangements allow customers to share tooling (like mask) and microelectronics wafer fabrication cost between several designs or projects.

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MPC consisting of five CMOS IC designs and few test N- and PMOS transistors for manufacturing acceptance MPC on Si.png
MPC consisting of five CMOS IC designs and few test N- and PMOS transistors for manufacturing acceptance

With the MPC arrangement, one chip is a combination of several designs and this combined chip is then repeated all over the wafer during the manufacturing. MPC arrangement produces typically roughly equal number of chip designs per wafer.

A wafer consisting of MPC designs all over the wafer and five process control monitor (PCM) designs for ensuring good quality of the processing A wafer consisting of MPC designs all over the wafer and five process control monitor (PCM) designs for ensuring good quality of the processing.jpg
A wafer consisting of MPC designs all over the wafer and five process control monitor (PCM) designs for ensuring good quality of the processing

With the MPW arrangement, different chip designs are aggregated on a wafer, with perhaps a different number of designs/projects per wafer. This is made possible with novel mask making and exposure systems in photolithography during IC manufacturing. MPW builds upon the older MPC procedures and enables more effective support for different phases and needs of manufacturing volumes of different designs/projects. MPW arrangement support education, research of new circuit architectures and structures, prototyping and even small volume production. [1] [2]

A multi-project wafer consisting of several different unequal number of designs/projects. MPW final.png
A multi-project wafer consisting of several different unequal number of designs/projects.

Worldwide, several MPW services are available from companies, semiconductor foundries and from government-supported institutions. Originally both MPC and MPW arrangements were introduced for integrated circuit (IC) education and research; some MPC/MPW services/gateways are aimed for non-commercial use only. Currently MPC/MPW services are effectively used for system on a chip integration. Selecting the right service platform at the prototyping phase ensures gradual scaling up production via MPW services taking into account the rules of the selected service.

MPC/MPW arrangements have also been applied to microelectromechanical systems (MEMS), [3] integrated photonics [4] like silicon photonics fabrication, flexible electronics, microfluidics and even chiplets. [5] [6]

A refinement of MPW is multi-layer mask (MLM) arrangement, where a limited number of masks (e.g. 4) are changed during manufacturing at exposure phase. The rest of the masks are the same from the chip to chip on the whole wafer. [7] MLM approach is well suited for several specific cases:

Typically MLM approach is used for one wafer batch (consisting of several wafers depending on the fabrication line) and for one customer. By using MLM it is possible to get larger devices (even up to wafer size) or larger number of dies and wafers up to few batches typically. MLM is a smooth continuation from MPW production volumes upwards and therefore this may support also small/mid size volume production. Not all foundries support MLM arrangements.

Due to the complexity of the technologies available and the need to run MPC/MPWs smoothly, following the rules, timing of the designs and use of suggested design tools are critical for leveraging the benefits of MPC/MPW services. However every service provider has its own practicalities including design data, die sizes, design rules, device models, design tools used, ready IP blocks available and timing etc.

Turn around times and cost of MPC and MPW services depend on the manufacturing technology and designs/prototypes are typically available as bare dies or as packaged devices. Deliveries are typically untested, but in most of the cases the quality of the manufacturing process is guaranteed by the measurement results of process control monitor(s) (PCM) or similar.

MPC approach was one of the first hardware service platforms in semiconductor industry, and the more flexible MPW arrangement is continuing to be part of well established microelectronics manufacturing and foundry model not limited to silicon IC manufacturing but spreading into other semiconductor production areas for cost effective prototyping, development and research.

Companies and services

Many MPC/MPW arrangements were first nationwide activities, but were expanded international, global co-operative activities based on emerging foundry technologies:

CMC Microsystems

CMC Microsystems is a not-for-profit organization in Canada accelerating research and innovation in advanced technologies. Founded in 1984, CMC lowers barriers to designing, manufacturing, and testing prototypes in microelectronics, photonics, quantum, MEMS, and packaging. CMC technology platforms such as the ESP (Electronic Sensor Platform) jumpstart R&D projects, enabling engineers and scientists to achieve results sooner and at a lower cost. Annually, more than 700 research teams from companies and 100 academic institutions around the world access CMC's services and turn more than 400 designs into prototypes through its global network of manufacturers. This support enables 400 industrial collaborations and 1,000 trained HQP to join industry each year, and these relationships assist in the translation of academic research into outcomes—publications, patents, and commercialization.

Muse Semiconductor

Muse Semiconductor was founded in 2018 [8] by former eSilicon employees. [9] [10] The company name "Muse" is an informal acronym for MPW University SErvice. [8] Muse focuses on serving the MPW needs of microelectronics researchers. [11] [12] Muse supports all TSMC technologies and offers an MPW service with a minimum area of 1mm^2 for some technologies. [13] [14] Muse is a member of the TSMC University FinFET Program. [15] [16]

MOSIS

The first well known MPC service was MOSIS (Metal Oxide Silicon Implementation Service), established by DARPA as a technical and human infrastructure for VLSI. MOSIS began in 1981 after Lynn Conway organized the first VLSI System Design Course at MIT in 1978 and the course produced 'multi-university, multi-project chip-design demonstration' [17] delivering devices to the course participants in 1979. [18] [19] The designs for the MPC were gathered using ARPANET. The technical background additionally to education was to develop and research in a cost effective way new computer architectures without limitations of standard components. [20] MOSIS primarily services commercial users with MPW arrangement. MOSIS has ended their University Support Program. [21] With MOSIS, designs are submitted for fabrication using either open (i.e., non-proprietary) VLSI layout design rules or vendor proprietary rules. Designs are pooled into common lots and run through the fabrication process at foundries. The completed chips (packaged or bare dies) are returned to customers.

NORCHIP

The first international silicon IC MPC service NORCHIP was established among four nordic countries (Denmark, Finland, Norway and Sweden) 1981 delivering first chips 1982. [22] It was funded by Nordic Industrial Fund and R&D financing organisations from each participating country. Targets were training and to enhance cooperation between research and industry specifically in areas of analog and digital signal processing and power management Integration. [23] Parallel with NORCHIP organised by same nordic countries there was Nordic GaAs program NOGAP 1986-1989, which produced modelling techniques for GaAs IC devices, and demonstrators of high speed digital and RF/analog MMICs. From 1989 to 1995 nordic universities, research institutes and small companies have been participating in european EUROCHIP and from 1995 on wards in EUROPRACTICE. [24] [25]

CMP

CMP a French company working since 1981 started MPC operation with NMOS offering but expanding offering to CMOS and various other technologies. [26] [27] CMP was also the first official pan-continental MPC/MPW operation having link to MOSIS among other MPW arrangements globally. CMPs services have included variety of technologies including multi-chip modules (MCMs) suitable for the packaging of chiplets. [28]

AusMPC

Similar arrangements utilising silicon IC technology were also AusMPC in Australia starting 1981, E.I.S. project (started year 1983) [29] in Germany and EUROEAST (1994-1997) covering Romania, Poland, Slovak Republic, Hungary, Czech Republic, Bulgaria, Estonia, Ukraine, Russia, Latvia, Lithuania and Slovenia. BERCHIP MPC activity starting in 1994 was organised in Latin America. Numerous MPW services have been launched since 1994 worldwide.

Efabless

Efabless enables a platform for ICs/SoCs designed by solely using open source design tools and community models. It started operations year 2020 as a start up with limited access to manufacturing technologies from SkyWater Technology and offering few annual runs as synched with US university academic year. [30] Within stabilised finansing and operations Efabless platform is targeted globally additionally to universities also for research institutes, small possibly start up phase companies and specifically as a first step to convert and test transition from FPGA to an integrated circuit.

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<span class="mw-page-title-main">Integrated circuit</span> Electronic circuit formed on a small, flat piece of semiconductor material

An integrated circuit (IC), also known as a microchip, computer chip, or simply chip, is a small electronic device made up of multiple interconnected electronic components such as transistors, resistors, and capacitors. These components are etched onto a small piece of semiconductor material, usually silicon. Integrated circuits are used in a wide range of electronic devices, including computers, smartphones, and televisions, to perform various functions such as processing and storing information. They have greatly impacted the field of electronics by enabling device miniaturization and enhanced functionality.

<span class="mw-page-title-main">Semiconductor device fabrication</span> Manufacturing process used to create integrated circuits

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as computer processors, microcontrollers, and memory chips. It is a multiple-step photolithographic and physico-chemical process during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

<span class="mw-page-title-main">Very-large-scale integration</span> Creating an integrated circuit by combining many transistors into a single chip

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining millions or billions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit chips were developed and then widely adopted, enabling complex semiconductor and telecommunication technologies. The microprocessor and memory chips are VLSI devices.

<span class="mw-page-title-main">Application-specific integrated circuit</span> Integrated circuit customized for a specific task

An application-specific integrated circuit is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficiency video codec. Application-specific standard product chips are intermediate between ASICs and industry standard integrated circuits like the 7400 series or the 4000 series. ASIC chips are typically fabricated using metal–oxide–semiconductor (MOS) technology, as MOS integrated circuit chips.

The foundry model is a microelectronics engineering and manufacturing business model consisting of a semiconductor fabrication plant, or foundry, and an integrated circuit design operation, each belonging to separate companies or subsidiaries.

MOSIS is multi-project wafer service that provides metal–oxide–semiconductor (MOS) chip design tools and related services that enable universities, government agencies, research institutes and businesses to prototype chips efficiently and cost-effectively.

Fabless manufacturing is the design and sale of hardware devices and semiconductor chips while outsourcing their fabrication to a specialized manufacturer called a semiconductor foundry. These foundries are typically, but not exclusively, located in the United States, China, and Taiwan. Fabless companies can benefit from lower capital costs while concentrating their research and development resources on the end market. Some fabless companies and pure play foundries may offer integrated-circuit design services to third parties.

In semiconductor manufacturing, silicon on insulator (SOI) technology is fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire. The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer and topmost silicon layer also vary widely with application.

Wafer fabrication is a procedure composed of many repeated sequential processes to produce complete electrical or photonic circuits on semiconductor wafers in semiconductor device fabrication process. Examples include production of radio frequency (RF) amplifiers, LEDs, optical computer components, and microprocessors for computers. Wafer fabrication is used to build components with the necessary electrical structures.

VLSI Technology, Inc., was an American company that designed and manufactured custom and semi-custom integrated circuits (ICs). The company was based in Silicon Valley, with headquarters at 1109 McKay Drive in San Jose. Along with LSI Logic, VLSI Technology defined the leading edge of the application-specific integrated circuit (ASIC) business, which accelerated the push of powerful embedded systems into affordable products.

<span class="mw-page-title-main">Integrated circuit design</span> Engineering process for electronic hardware

Integrated circuit design, semiconductor design, chip design or IC design, is a sub-field of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography.

The VLSI Project was a DARPA-program initiated by Robert Kahn in 1978 that provided research funding to a wide variety of university-based teams in an effort to improve the state of the art in microprocessor design, then known as Very Large Scale Integration (VLSI).

<span class="mw-page-title-main">Semiconductor fabrication plant</span> Factory where integrated circuits are manufactured

In the microelectronics industry, a semiconductor fabrication plant is a factory for semiconductor device fabrication.

The Mead–Conway VLSI chip design revolution, or Mead and Conway revolution, was a very-large-scale integration (VLSI) design revolution starting in 1978 which resulted in a worldwide restructuring of academic materials in computer science and electrical engineering education, and was paramount for the development of industries based on the application of microelectronics.

A three-dimensional integrated circuit is a MOS integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics.

GlobalFoundries Inc. is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, the company was privately owned by Mubadala Investment Company, a sovereign wealth fund of the United Arab Emirates, until an initial public offering (IPO) in October 2021.

Global Unichip Corporation (GUC) is a worldwide fabless ASIC design service company, with its headquarters located in the Hsinchu Science Park in Hsinchu, Taiwan.

WaferCatalyst is a Multi-Project Wafer (MPW) consolidation service by King Abdulaziz City for Science and Technology (KACST), Saudi Arabia. WaferCatalyst is a concept to silicon service and provides a number of tools for community building in the field of integrated circuit (IC) design. These include Multi-project wafer service fabrication, multi-layer mask (MLM), design support, consultancy services and fabrication support.

Glossary of microelectronics manufacturing terms

References

  1. ↑ Wu, M.-C.; Lin, R.-B. (2005). "Multiple Project Wafers for Medium-Volume IC Production". 2005 IEEE International Symposium on Circuits and Systems. pp. 4725–4728. doi:10.1109/ISCAS.2005.1465688. ISBN   0-7803-8834-8. S2CID   16510670.
  2. ↑ Noonan, J. A. (1986). "Investigation into methods and analysis of computer aided design of VLSI circuits". Master Thesis, the Department of Electrical and Electronic Engineering, the University of Adelaide.
  3. ↑ "EUROPRACTICE MEMS MPW".
  4. ↑ "MPW". SMART Photonics.
  5. ↑ "An integrated modular service for microfluidics, μBUILDER program".
  6. ↑ Grinde, C.; Welham, C. (2008). "μBUILDER: The easy and low cost road to advanced microsystems". 2008 15th IEEE International Conference on Electronics, Circuits and Systems. pp. 17–18. doi:10.1109/ICECS.2008.4675128. ISBN   978-1-4244-2181-7.
  7. ↑ Pann, P. (2009). "Prototyping and testing of analog integrated circuits". Proceedings - 1st Asia Symposium on Quality Electronic Design: 173–177. doi:10.1109/ASQED.2009.5206277. S2CID   2987670.
  8. 1 2 "FAQ | Muse Semiconductor". musesemi. Retrieved 2022-09-04.
  9. ↑ "FAQ | Muse Semiconductor". musesemi.
  10. ↑ McLellan, Paul. "Quoting Automatically the eSilicon Way". Semiwiki. Retrieved 2022-09-04.
  11. ↑ "Home | Muse Semiconductor". musesemi. Retrieved 2022-09-04.
  12. ↑ "Dear Colleague Letter: Supplements for Access to Semiconductor Fabrication (ASF) (nsf22113) | NSF - National Science Foundation". www.nsf.gov. Retrieved 2022-09-06.
  13. ↑ https://www.musesemi.com/shared-block-tapeout-pricing Example of MPW pricing
  14. ↑ https://www.csl.cornell.edu/~cbatten/pdfs/torng-brgtc2-slides-riscvday2018.pdf A New Era of Silicon Prototyping in Computer Architecture Research
  15. ↑ "TSMC University FinFET Program - Taiwan Semiconductor Manufacturing Company Limited" . Retrieved 30 March 2023.
  16. ↑ "TSMC University FinFET Program Services and Price | Muse Semiconductor".
  17. ↑ Conway, Lynn; Suchman, Lucy (February 28, 2021). "Conway-Suchman conversation". Conway Suchman Conversation– via conwaysuchman-conv.pubpub.org.
  18. ↑ "Lynn Conway's 1978 MIT VLSI System Design Course". ai.eecs.umich.edu.
  19. ↑ Conway, L. (1982). "The MPC adventures: Experiences with the generation of VLSI design and implementation methodologies" (PDF). Microprocessing and Microprogramming Number 4. 10 (4): 209–228. doi:10.1016/0165-6074(82)90054-0.
  20. ↑ "VLSI Implementation Services: From MPC79 to MOSIS and Beyond". ai.eecs.umich.edu.
  21. ↑ "MOSIS".
  22. ↑ Tenhunen, H.; Nielsen, I.-R. (1994). "Microelectronics R&D cooperation in the nordic countries". Analog Integrated Circuits and Signal Processing. 5 (3): 195–197. Bibcode:1994AICSP...5..195T. doi:10.1007/BF01261411. S2CID   62771908.
  23. ↑ Olesen, O.; Svensson, C. (1984). "NORCHIP, a silicon brokers model". Integration. 2: 3–13. doi:10.1016/0167-9260(84)90003-8.
  24. ↑ Kemppinen, E.; Järvinen, E.; Närhi, T. (1988). "Design of an L-band monolithic GaAs receiver front-end with low power consumption". 1988., IEEE International Symposium on Circuits and Systems. Vol. 3. pp. 2535–2538. doi:10.1109/ISCAS.1988.15458. S2CID   57998893.
  25. ↑ Andersson, M.; Åberg, M.; Pohjonen, H. (1988). "Simultaneous extraction of GaAs MESFET channel and gate diode parameters and its application to circuit simulation". 1988., IEEE International Symposium on Circuits and Systems. Vol. 3. pp. 2601–2604. doi:10.1109/ISCAS.1988.15474. S2CID   62628680.
  26. ↑ Courtois, B.; Delori, H.; Karam, J.M.; Paillotin, F.; Torki, K. (1996). "CMP services: Basic principles and developments". 2nd International Conference on ASIC. pp. 417–420. doi:10.1109/ICASIC.1996.562841. S2CID   108800823.
  27. ↑ Torki, K.; Courtois, B. (2001). "CMP: The access to advanced low cost manufacturing". Proceedings 2001 International Conference on Microelectronic Systems Education. pp. 6–9. doi:10.1109/MSE.2001.932392. ISBN   0-7695-1156-2. S2CID   30387757.
  28. ↑ Li, Tao; Hou, Jie; Yan, Jinli; Liu, Rulin; Yang, Hui; Sun, Zhigang (2020). "Chiplet Heterogeneous Integration Technology—Status and Challenges". Electronics. 9 (4): 670. doi: 10.3390/electronics9040670 . S2CID   218776269.
  29. ↑ "The E.I.S. Project and other EDA Achievements". xputers.informatik.uni-kl.de.
  30. ↑ "Google Partners with SkyWater and Efabless to Enable Open Source Manufacturing of Custom ASICs". Skywater Technology. 2020-11-12. Retrieved 2022-06-15.
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